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M390S3323ET1-C7C

Description
Synchronous DRAM Module, 32MX72, 5.4ns, CMOS, DIMM-168
Categorystorage    storage   
File Size100KB,10 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
Download Datasheet Parametric View All

M390S3323ET1-C7C Overview

Synchronous DRAM Module, 32MX72, 5.4ns, CMOS, DIMM-168

M390S3323ET1-C7C Parametric

Parameter NameAttribute value
MakerSAMSUNG
Parts packaging codeDIMM
package instructionDIMM,
Contacts168
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time5.4 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-XDMA-N168
memory density2415919104 bit
Memory IC TypeSYNCHRONOUS DRAM MODULE
memory width72
Number of functions1
Number of ports1
Number of terminals168
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32MX72
Package body materialUNSPECIFIED
encapsulated codeDIMM
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Certification statusNot Qualified
self refreshYES
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal locationDUAL
M390S3323ET1
M390S3323ET1 SDRAM DIMM
PC133 Registered DIMM
32Mx72 SDRAM DIMM with PLL & Register based on 16Mx8, 4Banks 4K Ref., 3.3V Synchronous DRAMs
GENERAL DESCRIPTION
The Samsung M390S3323ET1 is a 32M bit x 72 Synchronous
Dynamic RAM high density memory module. The Samsung
M390S3323ET1 consists of eighteen CMOS 16Mx8 bit Syn-
chronous DRAMs in TSOP-II 400mil packages, three 18-bits
Drive ICs for input control signal and one 2K EEPROM in 8-pin
TSOP package for Serial Presence Detect on a 168-pin glass-
epoxy substrate. One 0.22uF and one 0.0022uF decoupling
capacitors are mounted on the printed circuit board in parallel
for each SDRAM. The M390S3323ET1 is a Dual In-line Mem-
ory Module and is intented for mounting into 168-pin edge con-
nector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock-
cycle. Range of operating frequencies, programmable laten-
cies allows the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
FEATURE
• Performance range
Part No.
M390S3323ET1-C7C
M390S3323ET1-C7A
Max Freq. (Speed)
133MHz (7.5ns @ CL=2)
133MHz (7.5ns @ CL=3)
Burst mode operation
Auto & self refresh capability (4096 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
±
0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB :
Height (1,700mil),
double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front Pin
V
SS
DQ0
DQ1
DQ2
DQ3
V
D D
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
D D
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
V
D D
WE
DQM0
Front
Pin
Front
DQ18
DQ19
V
DD
DQ20
NC
*V
R E F
CKE1
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
*CLK2
NC
NC
**SDA
**SCL
V
DD
Pin
Back
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
CS1
RAS
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
D D
*CLK1
*A12
V
SS
CKE0
CS3
DQM6
DQM7
*A13
V
D D
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
Pin
Back
29 DQM1 57
58
30
CS0
31
DU
59
32
V
SS
60
33
A0
61
34
A2
62
35
A4
63
36
A6
64
37
A8
65
38 A10/AP 66
39
BA1
67
40
V
D D
68
69
41
V
D D
42 CLK0 70
71
43
V
SS
72
44
DU
73
45
CS2
46 DQM2 74
47 DQM3 75
48
DU
76
49
V
D D
77
50
NC
78
51
NC
79
52
CB2
80
53
CB3
81
54
V
SS
82
55 DQ16 83
56 DQ17 84
PIN NAMES
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
CB0 ~ 7
CLK0
CKE0 ~ 1
CS0 ~ CS3
RAS
CAS
WE
DQM0 ~ 7
V
D D
V
SS
*V
REF
REGE
SDA
SCL
SA0 ~ 2
DU
NC
Function
Address input (Multiplexed)
Select bank
Data input/output
Check bit (Data-in/data-out)
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
DQM
Power supply (3.3V)
Ground
Power supply for reference
Register enable
Serial data I/O
Serial clock
Address in EEPROM
Don′t use
No connection
85
V
SS
86 DQ32
87 DQ33
88 DQ34
89 DQ35
90
V
DD
91 DQ36
92 DQ37
93 DQ38
94 DQ39
95 DQ40
96
V
SS
97 DQ41
98 DQ42
99 DQ43
100 DQ44
101 DQ45
102
V
DD
103 DQ46
104 DQ47
105 CB4
106 CB5
107
V
SS
108
NC
109
NC
110
V
DD
111 CAS
112 DQM4
141 DQ50
142 DQ51
143
V
DD
144 DQ52
145
NC
146 *V
REF
147 REGE
148
V
SS
149 DQ53
150 DQ54
151 DQ55
152
V
SS
153 DQ56
154 DQ57
155 DQ58
156 DQ59
157
V
DD
158 DQ60
159 DQ61
160 DQ62
161 DQ63
162
V
SS
163 *CLK3
164
NC
165 **SA0
166 **SA1
167 **SA2
168
V
DD
* These pins are not used in this module.
**
These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.0 Nov. 2002
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