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M471B5273CH0-YH9

Description
DDR DRAM Module, 512MX64, 0.255ns, CMOS, SODIMM-204
Categorystorage    storage   
File Size1001KB，36 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
Environmental Compliance
Download Datasheet Parametric Compare View All

M471B5273CH0-YH9 Overview

DDR DRAM Module, 512MX64, 0.255ns, CMOS, SODIMM-204

M471B5273CH0-YH9 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSAMSUNG
package instructionDIMM, DIMM204,24
Reach Compliance Codeunknown
access modeDUAL BANK PAGE BURST
Maximum access time0.255 ns
Other featuresAUTO/SELF REFRESH; ALSO OPERATES AT 1.5V SUPPLY; WD-MAX
Maximum clock frequency (fCLK)667 MHz
I/O typeCOMMON
JESD-30 codeR-XDMA-N204
length67.6 mm
memory density34359738368 bit
Memory IC TypeDDR DRAM MODULE
memory width64
Number of functions1
Number of ports1
Number of terminals204
word count536870912 words
character code512000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature
organize512MX64
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeDIMM
Encapsulate equivalent codeDIMM204,24
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
power supply1.35 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height30.15 mm
self refreshYES
Maximum standby current0.192 A
Maximum slew rate1.8 mA
Maximum supply voltage (Vsup)1.45 V
Minimum supply voltage (Vsup)1.283 V
Nominal supply voltage (Vsup)1.35 V
surface mountNO
technologyCMOS
Temperature levelOTHER
Terminal formNO LEAD
Terminal pitch0.6 mm
Terminal locationDUAL
width3.8 mm

M471B5273CH0-YH9 Preview

Rev. 1.31, Jul. 2012
M471B5773CHS
M471B5273CH0
204pin Unbuffered SODIMM
based on 2Gb C-die
1.35V
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ
2012 Samsung Electronics Co., Ltd. All rights reserved.
-1-
Unbuffered SODIMM
datasheet
History
Draft Date
Dec. 2009
Jan. 2010
Rev. 1.31
DDR3L SDRAM
Revision History
Revision No.
1.0
1.1
- First Release
- Changed DIMM IDD Definition
- Added DIMM IDD Specification
- Deleted operation frequency of 800Mbps 6-6-6
1.2
1.3
1.31
- Added "CL5" to supported CL setting
- Added 1600Mbps product form product list
- Corrected Typo
Feb. 2010
Jun. 2012
Jul. 2012
-
-
-
S.H.Kim
J.Y.Lee
J.Y.Lee
Remark
-
-
Editor
S.H.Kim
S.H.Kim
-2-
Unbuffered SODIMM
datasheet
Rev. 1.31
DDR3L SDRAM
Table Of Contents
204pin Unbuffered SODIMM based on 2Gb C-die
1. DDR3L Unbuffered SODIMM Ordering Information...................................................................................................... 4
2. Key Features................................................................................................................................................................. 4
3. Address Configuration .................................................................................................................................................. 4
4. x64 DIMM Pin Configurations (Front side/Back Side)................................................................................................... 5
5. Pin Description ............................................................................................................................................................. 6
6. Input/Output Functional Description.............................................................................................................................. 7
7. Function Block Diagram: ............................................................................................................................................... 8
7.1 2GB, 256Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ..................................................................... 8
7.2 4GB, 512Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................................... 9
8. Absolute Maximum Ratings .......................................................................................................................................... 10
8.1 Absolute Maximum DC Ratings............................................................................................................................... 10
8.2 DRAM Component Operating Temperature Range ................................................................................................ 10
9. AC & DC Operating Conditions..................................................................................................................................... 10
9.1 Recommended DC Operating Conditions .............................................................................................................. 10
10. AC & DC Input Measurement Levels .......................................................................................................................... 11
10.1 AC & DC Logic Input Levels for Single-ended Signals .......................................................................................... 11
10.2 V
REF
Tolerances.................................................................................................................................................... 13
10.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 14
10.3.1. Differential Signals Definition ......................................................................................................................... 14
10.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. 14
10.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 16
10.3.4. Differential Input Cross Point Voltage ............................................................................................................ 17
10.4 Slew Rate Definition for Single Ended Input Signals ............................................................................................. 18
10.5 Slew rate definition for Differential Input Signals ................................................................................................... 18
11. AC & DC Output Measurement Levels ....................................................................................................................... 18
11.1 Single Ended AC and DC Output Levels............................................................................................................... 18
11.2 Differential AC and DC Output Levels ................................................................................................................... 18
11.3 Single-ended Output Slew Rate ............................................................................................................................ 19
11.4 Differential Output Slew Rate ................................................................................................................................ 20
12. IDD specification definition.......................................................................................................................................... 21
13. IDD SPEC Table ......................................................................................................................................................... 23
14. Input/Output Capacitance ........................................................................................................................................... 24
14.1 1Rx8 2GB SoDIMM ............................................................................................................................................... 24
14.2 2Rx8 4GB SoDIMM ............................................................................................................................................... 24
15. Electrical Characteristics and AC timing ..................................................................................................................... 25
15.1 Refresh Parameters by Device Density................................................................................................................. 25
15.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 25
15.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 25
15.3.1. Speed Bin Table Notes .................................................................................................................................. 29
16. Timing Parameters by Speed Grade .......................................................................................................................... 30
16.1 Jitter Notes ............................................................................................................................................................ 33
16.2 Timing Parameter Notes........................................................................................................................................ 34
17. Physical Dimensions : ................................................................................................................................................. 35
17.1 256Mbx8 based 256Mx64 Module (1 Rank) - M471B5773CHS ........................................................................... 35
17.2 256Mbx8 based 512Mx64 Module (2 Ranks) - M471B5273CH0 .......................................................................... 36
-3-
Unbuffered SODIMM
datasheet
Density
2GB
4GB
Organization
256Mx64
512Mx64
Component Composition
256Mx8(K4B2G0846C-HY##)*8
256Mx8(K4B2G0846C-HY##)*16
Rev. 1.31
DDR3L SDRAM
Number of
Rank
1
2
Height
30mm
30mm
1. DDR3L Unbuffered SODIMM Ordering Information
Part Number
M471B5773CHS-YF8/H9/K0
M471B5273CH0-YF8/H9/K0
NOTE
:
1. "##" - F8/H9/K0
2. F8 - 1066Mbps 7-7-7 / H9 - 1333Mbps 9-9-9 / K0 - 1600Mbps 11-11-11
- DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)
- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)
2. Key Features
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DDR3-800
6-6-6
2.5
6
15
15
37.5
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
DDR3-1600
11-11-11
1.25
11
13.75
13.75
35
48.75
Unit
ns
nCK
ns
ns
ns
ns
JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Power Supply
V
DDQ
= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
400 MHz f
CK
for 800Mb/sec/pin, 533MHz f
CK
for 1066Mb/sec/pin, 667MHz f
CK
for 1333Mb/sec/pin, 800MHz f
CK
for 1600Mb/sec/pin
8 independent internal bank
Programmable CAS Latency: 5,6,7,8,9,10,11
Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)
8-bit pre-fetch
Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
Bi-directional Differential Data Strobe
Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower then T
CASE
85°C, 3.9us at 85°C < T
CASE
≤
95°C
Asynchronous Reset
3. Address Configuration
Organization
256Mx8(2Gb) based Module
Row Address
A0-A14
Column Address
A0-A9
Bank Address
BA0-BA2
Auto Precharge
A10/AP
-4-
Unbuffered SODIMM
datasheet
Back
V
SS
DQ4
DQ5
V
SS
DQS0
DQS0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
RESET
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DQS3
DQS3
V
SS
DQ30
DQ31
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
CKE0
V
DD
NC
BA2
V
DD
A12/BC
A9
V
DD
A8
A5
V
DD
A3
A1
V
DD
CK0
CK0
V
DD
A10/AP
BA0
V
DD
WE
CAS
V
DD
A13
3
S1
V
DD
TEST
V
SS
DQ32
DQ33
V
SS
DQS4
DQS4
Rev. 1.31
DDR3L SDRAM
4. x64 DIMM Pin Configurations (Front side/Back Side)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
50
53
55
57
59
61
63
65
67
69
Front
V
REFDQ
V
SS
DQ0
DQ1
V
SS
DM0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
V
SS
DQ26
DQ27
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
Pin
71
Front
V
SS
KEY
Pin
72
Back
V
SS
Pin
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
Front
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SA0
V
DDSPD
SA1
V
TT
Pin
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
Back
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS5
DQS5
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7
DQS7
V
SS
DQ62
DQ63
V
SS
NC
SDA
SCL
V
TT
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
CKE1
V
DD
A15
3
A14
3
V
DD
A11
A7
V
DD
A6
A4
V
DD
A2
A0
V
DD
CK1
CK1
V
DD
BA1
RAS
V
DD
S0
ODT0
V
DD
ODT1
NC
V
DD
V
REFCA
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
NOTE
:
1. NC = No Connect, NU = Not Usable, RFU = Reserved Future Use
2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
-5-
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M471B5273CH0-YH9 Related Products

M471B5273CH0-YH9 M471B5773CHS-YH9 M471B5773CHS-YF8 M471B5273CH0-YF8
Description DDR DRAM Module, 512MX64, 0.255ns, CMOS, SODIMM-204 DDR DRAM Module, 256MX64, 0.255ns, CMOS, SODIMM-204 DDR DRAM Module, 256MX64, 0.3ns, CMOS, SODIMM-204 DDR DRAM Module, 512MX64, 0.3ns, CMOS, SODIMM-204
Is it Rohs certified? conform to conform to conform to conform to
Maker SAMSUNG SAMSUNG SAMSUNG SAMSUNG
package instruction DIMM, DIMM204,24 DIMM, DIMM204,24 DIMM, DIMM204,24 DIMM, DIMM204,24
Reach Compliance Code unknown unknown unknown unknow
access mode DUAL BANK PAGE BURST SINGLE BANK PAGE BURST SINGLE BANK PAGE BURST DUAL BANK PAGE BURST
Maximum access time 0.255 ns 0.255 ns 0.3 ns 0.3 ns
Other features AUTO/SELF REFRESH; ALSO OPERATES AT 1.5V SUPPLY; WD-MAX AUTO/SELF REFRESH; ALSO OPERATES AT 1.5V SUPPLY; WD-MAX AUTO/SELF REFRESH; ALSO OPERATES AT 1.5V SUPPLY; WD-MAX AUTO/SELF REFRESH; ALSO OPERATES AT 1.5V SUPPLY; WD-MAX
Maximum clock frequency (fCLK) 667 MHz 667 MHz 533 MHz 533 MHz
I/O type COMMON COMMON COMMON COMMON
JESD-30 code R-XDMA-N204 R-XDMA-N204 R-XDMA-N204 R-XDMA-N204
length 67.6 mm 67.6 mm 67.6 mm 67.6 mm
memory density 34359738368 bit 17179869184 bit 17179869184 bit 34359738368 bi
Memory IC Type DDR DRAM MODULE DDR DRAM MODULE DDR DRAM MODULE DDR DRAM MODULE
memory width 64 64 64 64
Number of functions 1 1 1 1
Number of ports 1 1 1 1
Number of terminals 204 204 204 204
word count 536870912 words 268435456 words 268435456 words 536870912 words
character code 512000000 256000000 256000000 512000000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C
organize 512MX64 256MX64 256MX64 512MX64
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE
Package body material UNSPECIFIED UNSPECIFIED UNSPECIFIED UNSPECIFIED
encapsulated code DIMM DIMM DIMM DIMM
Encapsulate equivalent code DIMM204,24 DIMM204,24 DIMM204,24 DIMM204,24
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY
power supply 1.35 V 1.35 V 1.35 V 1.35 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
refresh cycle 8192 8192 8192 8192
Maximum seat height 30.15 mm 30.15 mm 30.15 mm 30.15 mm
self refresh YES YES YES YES
Maximum standby current 0.192 A 0.096 A 0.096 A 0.192 A
Maximum slew rate 1.8 mA 1.56 mA 1.32 mA 1.52 mA
Maximum supply voltage (Vsup) 1.45 V 1.45 V 1.45 V 1.45 V
Minimum supply voltage (Vsup) 1.283 V 1.283 V 1.283 V 1.283 V
Nominal supply voltage (Vsup) 1.35 V 1.35 V 1.35 V 1.35 V
surface mount NO NO NO NO
technology CMOS CMOS CMOS CMOS
Temperature level OTHER OTHER OTHER OTHER
Terminal form NO LEAD NO LEAD NO LEAD NO LEAD
Terminal pitch 0.6 mm 0.6 mm 0.6 mm 0.6 mm
Terminal location DUAL DUAL DUAL DUAL
width 3.8 mm 3.8 mm 3.8 mm 3.8 mm

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