EEWORLDEEWORLDEEWORLD

Part Number

Search

DW-26-15-G-T-200

Description
Board Stacking Connector, 78 Contact(s), 3 Row(s), Male, Straight, Solder Terminal,
CategoryThe connector    The connector   
File Size1MB,1 Pages
ManufacturerSAMTEC
Websitehttp://www.samtec.com/
Environmental Compliance  
Download Datasheet Parametric View All

DW-26-15-G-T-200 Overview

Board Stacking Connector, 78 Contact(s), 3 Row(s), Male, Straight, Solder Terminal,

DW-26-15-G-T-200 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSAMTEC
Reach Compliance Codecompliant
body width0.296 inch
subject depth0.2 inch
body length2.6 inch
Connector typeBOARD STACKING CONNECTOR
Contact to complete cooperationGOLD (10)
Contact completed and terminatedGOLD (3)
Contact point genderMALE
Contact materialPHOSPHOR BRONZE
contact modeRECTANGULAR
Contact styleSQ PIN-SKT
DIN complianceNO
Filter functionNO
IEC complianceNO
Insulator colorBLACK
insulator materialGLASS FILLED POLYESTER
JESD-609 codee4
MIL complianceNO
Manufacturer's serial numberDW
Plug contact pitch0.1 inch
Mixed contactsNO
Installation methodSTRAIGHT
Installation typeBOARD
PCB row number3
Number of rows loaded3
OptionsGENERAL PURPOSE
Terminal pitch2.54 mm
Termination typeSOLDER
Total number of contacts78
UL Flammability Code94V-0
Keil5 only successfully added .c files, but failed to add .h files. What should I do?
I need help. When I modified the program, I called a new function, so I added a new file. However, after adding, only the .c file was successfully added, and the .h file could not be added. Moreover, ...
zhuuu Integrated technical exchanges
Altera Reference Design-CORDIC Reference Design
IntroductionThe co-ordinate rotation digital computer (CORDIC) reference design implements the CORDIC algorithm, which converts cartesian to polar coordinates and vice versa and also allows vectors to...
xiaoxin1 FPGA/CPLD
[Xiao Meige SOPC Learning Notes] Altera SOPC Embedded System Design Tutorial
[i=s]This post was last edited by Xinhangxian Paotang on 2017-4-12 11:01[/i] [align=center][color=#000][size=15px][size=5][b]Altera SOPC Embedded System Design Tutorial[/b][b]Chapter 1 Overview[/b][/s...
芯航线跑堂 FPGA/CPLD
EEWORLD University ---- MSP430 instruction system
MSP430 instruction system : https://training.eeworld.com.cn/course/349...
dongcuipin MCU
Design of HDB3 Codec Based on FPGA
1 Encoder Design Since VHDL cannot handle negative levels and can only face the two states of "1" and "0", its output needs to be encoded, as shown in Table 1. The encoding is implemented by encoding ...
led123 FPGA/CPLD
CD4046 locks the power grid 50hz phase-locked loop circuit
I use CD4046 and CD4040 (256 frequency division) to phase lock the grid frequency of 50Hz, but I can't adjust it. I don't know the following frequencies: f0: center frequency = 50Hz*256=12.8kHz? ? 2fc...
yilaozhuang Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2840  2635  1865  2722  2834  58  54  38  55  23 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号