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TLC
Devices Included in this Data Sheet:
•
TLC154/155/156/157 : EPROM devices
•
TLC154/155/156/157 : Mask ROM devices
TLC156
EPROM/ROM-Based 8-Bit Microcontroller Series
FEATURES
•
Only 42 single word instructions
•
All instructions are single cycle except for program branches which are two-cycle
•
13-bit wide instructions
•
8-bit wide data path
•
5-level deep hardware stack
•
Operating speed: DC-20 MHz clock input
DC-100 ns instruction cycle
Device
TLC154
TLC155
TLC156
Pins #
18
28
18
I/O #
12
20
12
EPROM/ROM (Byte)
512
512
1K
RAM (Byte)
49
48
49
28
TLC157
20
2K
96
•
Direct, indirect addressing modes for data accessing
•
8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler
•
Internal Power-on Reset (POR)
•
Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)
•
Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)
•
On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog
enable/disable control
•
Three I/O ports IOA, IOB and IOC with independent direction control
•
Soft-ware I/O pull-high/pull-down or open-drain control
•
One internal interrupt source: Timer0 overflow; Two external interrupt source: INT pin, Port B input change
•
Wake-up from SLEEP by INT pin or Port B input change
•
Power saving SLEEP mode
•
Programmable Code Protection
•
Selectable oscillator options:
- RC: Resistor/Capacitor Oscillator
- XT: Crystal/Resonator Oscillator
- HF: High Frequency Crystal/Resonator Oscillator
- LF: Low Frequency Crystal Oscillator
•
Wide-operating voltage range:
- EPROM : 2.3V to 5.5V
- ROM : 2.3V to 5.5V
This datasheet contains new product inform99032685ation. TLC reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Rev0.95 Nov 20, 2003
P.1/TLC156
TLC
GENERAL DESCRIPTION
TLC156
The TLC156 series is a family of low-cost, high speed, high noise immunity, EPROM/ROM-based 8-bit CMOS
microcontrollers. It employs a RISC architecture with only 42 instructions. All instructions are single cycle except
for program branches which take two cycles. The easy to use and easy to remember instruction set reduces
development time significantly.
The TLC156 series consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer (PWRT),
Oscillator Start-up Timer(OST), Watchdog Timer, EPROM/ROM, SRAM, tri-state I/O port, I/O
pull-high/open-drain/pull-down control, Power saving SLEEP mode, real time programmable clock/counter,
Interrupt, Wake-up from SLEEP mode, and Code Protection for EPROM products. There are four oscillator
configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator.
The TLC154 and TLC155 address 512×13 of program memory, the TLC156 address 1K×13 of
program memory, and the TLC157 address 2K×13 of program memory.
The TLC156 can directly or indirectly address its register files and data memory. All special function registers
including the program counter are mapped in the data memory.
BLOCK DIAGRAM
Oscillator
Circuit
5-level
STACK
Watchdog
Timer
Program
Counter
FSR
SRAM
ALU
EPROM
/ ROM
Instruction
Decoder
PORTA
PORTB
Interrupt
Control
Timer0
Accumulator
PORTC
Rev0.95 Nov 20, 2003
P.2/TLC156
TLC
PIN CONNECTION
PDIP, SOP
IOA2
IOA3
T0CKI
RSTB
Vss
IOB0/INT
IOB1
IOB2
IOB3
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
IOA1
IOA0
OSCI
OSCO
Vdd
IOB7
IOB6
IOB5
IOB4
TLC156
SSOP
IOA2
IOA3
T0CKI
RSTB
Vss
Vss
IOB0/INT
IOB1
IOB2
IOB3
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
IOA1
IOA0
OSCI
OSCO
Vdd
Vdd
IOB7
IOB6
IOB5
IOB4
TLC154
TLC156
TLC154
TLC156
PDIP, SOP
T0CKI
Vdd
NC
Vss
NC
IOA0
IOA1
IOA2
IOA3
IOB0/INT
IOB1
IOB2
IOB3
IOB4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RSTB
OSCI
OSCO
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
IOB7
IOB6
IOB5
SSOP
Vss
T0CKI
Vdd
Vdd
IOA0
IOA1
IOA2
IOA3
IOB0/INT
IOB1
IOB2
IOB3
IOB4
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RSTB
OSCI
OSCO
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
IOB7
IOB6
IOB5
TLC155
TLC157
TLC155
TLC157
PIN DESCRIPTIONS
Name
IOA0 ~ IOA3
IOB0/INT
IOB1 ~ IOB7
IOC0 ~ IOC7
I/O
I/O
I/O
I/O
I/O
Description
IOA0 ~ IOA3 as bi-direction I/O port
Bi-direction I/O pin with system wake-up function / External interrupt input
Bi-direction I/O port with system wake-up function
Bi-direction I/O port
Clock input to Timer0. Must be tied to Vss or Vdd, if not in use, to reduce current
T0CKI
I
consumption
RSTB
I
System clear (RESET) input. This pin is an active low RESET to the device.
X’ type: Oscillator crystal input
tal
OSCI
I
RC type: Clock input of RC oscillator
X’ type: Oscillator crystal output.
tal
OSCO
O
RC mode: Outputs with the instruction cycle rate
Vdd
-
Positive supply
Vss
-
Ground
Legend: I=input, O=output, I/O=input/output
Rev0.95 Nov 20, 2003
P.2/TLC156
TLC
1.0 MEMORY ORGANIZATION
TLC156 memory is organized into program memory and data memory.
TLC156
1.1 Program Memory Organization
The TLC154/155 have a 9-bit Program Counter (PC) capable of addressing a 512×13 program memory
space. The TLC156 have a 10-bit Program Counter capable of addressing a 1K×13 program memory space.
The TLC157 have an 11-bit Program Counter capable of addressing a 2K×13 program memory space.
The RESET vector for the TLC154/155 is at 1FFh. The RESET vector for the TLC156 is at 3FFh. The
RESET vector for the TLC157 is at 7FFh.
The H/W interrupt vector is at 008h. And the S/W interrupt vector is at 002h.
TLC157 has program memory size greater than 1K words, but the CALL and GOTO instructions only have a
10-bit address range. This 10-bit address range allows a branch within a 1K program memory page size. To allow
CALL and GOTO instructions to address the entire 2K program memory address range for TLC157, there is
another one bit to specify the program memory page. This paging bit comes from the PCHBUF<2> bit. When doing
a CALL or GOTO instruction, the user must ensure that page bit PCHBUF<2> are programmed so that the desired
program memory page is addressed. When one of the return instructions is executed, the entire 11-bit PC is POPed
from the stack. Therefore, manipulation of the PCHBUF <2> is not required for the return instructions.
FIGURE 1.1: Program Memory Map and STACK
PC<10:0>
PC<9:0>
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
7FFh
Reset Vector
PC<8:0>
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
3FFh
Reset Vector
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
1FFh
:
:
008h H/W Interrupt Vector
002h S/W Interrupt Vector
000h
TLC154/155
Reset Vector
:
:
:
:
008h H/W Interrupt Vector
002h S/W Interrupt Vector
000h
TLC156
008h H/W Interrupt Vector
002h S/W Interrupt Vector
000h
TLC157
Rev0.95 Nov 20, 2003
P.2/TLC156
TLC
TLC156
1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the
operation of the device.
In TLC157, the data memory is partitioned into four banks. Switching between these banks requires the RP1
and RP0 bits in the FSR register to be configured for the desired bank.
TABLE 1.1: Operational Registers Map
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
N/A (w)
OPTION
-
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
N/A (w)
IOSTA
Port A I/O Control Register
N/A (w)
IOSTB
Port B I/O Control Register
N/A (w)
IOSTC
Port C I/O Control Register
00h (r/w)
INDF
Uses contents of FSR to address data memory (not a physical register)
01h (r/w)
TMR0
8-bit real-time clock/counter
02h (r/w)
PCL
Low order 8 bits of PC
03h (r/w)
STATUS
GP2
GP1
GP0
TO
PD
Z
DC
C
(3)
(3)
04h (r/w)
FSR
RP1
RP0
Indirect data memory address pointer
05h (r/w)
PORTA
-
-
-
-
IOA3
IOA2
IOA1
IOA0
06h (r/w)
PORTB
IOB7
IOB6
IOB5
IOB4
IOB3
IOB2
IOB1
IOB0
(1)
07h (r/w)
PORTC
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
08h (r/w)
PCON
WDTE
EIS
LVDTE
ROC
-
-
-
-
09h (r/w)
WUCON
WUB7
WUB6
WUB5
WUB4
WUB3
WUB2
WUB1
WUB0
(2)
0Ah (r/w) PCHBUF
-
-
-
-
-
Upper 3 bits Buffer of PC
0Bh (r/w)
PDCON
/PDB3
/PDB2
/PDB1
/PDB0
/PDA3
/PDA2
/PDA1
/PDA0
0Ch (r/w)
ODCON
ODB7
ODB6
ODB5
ODB4
ODB3
ODB2
ODB1
ODB0
0Dh (r/w)
PHCON
/PHB7
/PHB6
/PHB5
/PHB4
/PHB3
/PHB2
/PHB1
/PHB0
0Eh (r/w)
INTEN
GIE
-
-
-
-
INTIE
PBIE
T0IE
0Fh (r/w)
INTFLAG
-
-
-
-
-
INTIF
PBIF
T0IF
Legend: - = unimplemented, read as ‘ ,
0’
Note 1 : PORTC is an 8-bit I/O Register for TLC155/157.
PORTC is a General Purpose Register for TLC154/156.
2 : There is only 1 bit in TLC154/155. There are only 2 bits in TLC156. And there are 3 bits in
TLC157.
3 : For TLC154/155/156, these bits are not used, read as ‘
1’
Rev0.95 Nov 20, 2003
P.2/TLC156
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