Hynix semiconductor
INTRODUCTION
From now on, you can hook your product onto the inter-net directly.
Put the PC aside, HMS91C7432 do all the jobs that the PC do for
inter-net connection.
HMS91C7432 is a CMOS IC with a complete TCP/IP protocol suite to facilitate
inter-net connection for embedded application. The built-in email engine can
transform any ASCII message to standard email format. It sends and receives
email; conduct the whole log on process automatically. Built-in PPP protocol
handle user-ISP handshaking and authentication process automatically. The
HMS91C7432 also includes the MODEM driver, no code should write to drive
the MODEM (parameter of modem must be transferred by the host to make
HMS91C7432 works with your modem).
Using HMS91C7432 is easy, a simple 8 bit parallel port (8 bit data plus 4
control lines) bridge the IC with your application. A serial DTE port is ready for
directly connect to an onboard modem or through DTE interface to a serial
modem.
Make your product inter-net able, just add an HMS91C7432 on your BOM.
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Hynix semiconductor
HMS91C7432 features and functions
Implementation of the complete TCP/IP protocol suite
Built-in Email sending and reception function.
Standard SMTP protocol stack.
Standard POP3 protocol stack.
Standard PPP protocol stack to facilitate dial-up network log on.
Standard DNS protocol stack, resolve URL with dynamic DNS server.
Serial modem driver built-in.
Support V.90 56Kflex modem or lower.
8 bit parallel interface to the user application.
Serial DTE port for ease of modem interface.
5V or 3.3V operation voltage
20 pins SOP package
Detail description of HMS91C7432 function and its application
TCP/IP protocol suite is the key to inter-net
access. Email; Home Page materials and all
the data traffic on the inter-net are carry out
by using the TCP/IP well defined format.
Time before HMS91C7432 exist, most
inter-net connection were to be handled by
the PC. Hand held devices and equipments
must be attached to the PC to get access to
the inter-net. Now the era of “PC-free”
inter-net connection has come. With
HMS91C7432, you can make your product
be able to send and receive email; surf on
the WWW and even “TALK” to another
device through the inter-net, by just plugging
the telephone line onto it.
The core of the HMS91C7432 is a complete
TCP/IP protocol suite. Files and messages
pass to the HMS91C7432 will be
transformed into the appropriate format and
packets to conform the inter-net standard.
This transformation is transparent to the
user’s application.
On top of the TCP/IP core, there is an Email
engine built-in. User’s program just needed
to inform the HMS91C7432 an email is
going to send and follow with the email body.
HMS91C7432 will then wake up the modem
and dial the ISP to log on the mail server.
The mail will be sent when log on has
success. HMS91C7432 complete this whole
process fully automatic.
Reception of Email is as simple as getting
email on the PC. The application program
send a “Receive Email” command to the
HMS91C7432, it dial up the ISP and log on
the server, then it check and download any
email automatically. Each message will be
stored in the RAM buffer, HMS91C7432 will
notify the application program an email has
come and waiting for retrieve.
The built-in PPP module handles the “Log
on process”. This is a standard protocol to
pass the user’s account ID and the
password to the ISP. This module handles
the authentication and “Handshaking”.
User’s program just pass the user’s ID and
password to HMS91C7432 and the PPP do
it all.
HMS91C7432 (later version only) also equip
with a FTP module to facilitate file transfer
and file downloading from the FTP site. This
function is especially good for remote
system update and game download for
hand-held game inter-net access.
The standard serial DTE interface on the
HMS91C7432 ease the modem connection.
The built-in modem driver support V.90 and
56K flex dual modem or lower.
HMS91C7432 is controlled by an 8 bit
data/command port. This port accepts
command passed by the host MCU.
Incoming and outgoing message will be
passed between the host and the
HMS91C7432 through this port as well.
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Hynix semiconductor
Specifications of HMS91C7432
The HMS91C7432 TCP/IP communication controller is manufactured in advance CMOS
process.
The HMS91C7432 implement complete TCP/IP protocol suite includes PPP; IP; ICMP;TCP;
UDP; DNS; SMTP; POP3 protocol and additionally a general MODEM driver.
The HMS91C7432 is built-in with 96Kb SRAM (12K x 8) for communication and buffering, A
full duplex UART as DTE for ease of serial modem connection.
The HMS91C7432 has an 8 bits Data/Command port and 4 control pins to facilitate control
and communication between the Host MCU and the modem. There are only 20 simple
commands, each of which is a single byte long, to establish and to complete the whole
internet communication. 45 respond codes for the Host MCU to monitor the communication
status.
Extremely low external component count. Very low power consumption.
Features :
Implement TCP/IP protocol suit.
SMTP for sending email
POP3 for receiving email
PPP for dialup network log on
and hand shaking.
DNS protocol to resolve IP
address from URL
Full static operation
Test
Full Duplex 56K/115Kbps UART
VCC
port
for
modem
DTE
connection.
Speed range up to 22.118MHz
8 bits Bi-directional Data/Command bus.
Modem driver included
Power control modes
Active mode
Power-down mode
Dissipating Current
Active 25mA
Power-down 10uA max.
20 single byte easy commands
45 respond codes
Package type 20-SOP
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
10
HMS91C743
2
SOP 20
20
19
18
17
16
15
14
13
12
11
RXD
TXD
Reset
Strobe
WR
INT
Wait
Xtal 2
Xtal 1
Vss
Operating voltage
Dissipating Current
Active mode
Power down mode
Oscillation Frequency
Operating Temperature
Storage Temperature
3.3V +/- 10%
25 mA
10uA max.
11.0592 Mhz
-40 to +85°C
-65 to +150°C
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Hynix semiconductor
Specifications of HMS91C7432
MNEMONIC
Vss
Vcc
D0 to D7
PIN
14
10
1–8
TYPE
NAME AND FUNCTION
Ground :
0V reference.
Power Supply :
This is the power supply voltage for
normal, and power-down operation.
Data/Command Port :
This is an 8 bit bi-directional I/O
port with internal pull-ups. This port is for data transfer
between Host MCU, it also serves as command
reception and responds code issuance port from and to
the Host MCU.
WAIT :
Handshake signal. When low it indicates that is
OK to start a cycle (assert a strobe), when high it
indicates that it is OK to end the cycle (de-assert a
strobe).
INT :
Active LOW Output a request to the Host MCU if
data/respond code are to be sent.
WRITE :
Active LOW write enable pin. Set this pin LOW
for a write cycle. Set this pin HIGH for a read cycle.
STROBE :
Data strobe signal. Active low indicates a
Data_Read or Data_Write operation is in process.
RXD :
UART serial input port.
TXD :
UART serial output port.
RESET :
A high level on this pin for 2us while the
oscillator is running resets the device.
TEST :
Test pin, should be stuck at zero when normal
operation.
XTAL1 :
Input to the inverting oscillator amplifier and
input to the internal clock generator circuits.
XTAL2 :
Output to the inverting oscillator amplifier.
I/O
WAIT
14
Out
INT
WR
STROBE
RXD
TXD
RESET
TEST
XTAL 1
XTAL 2
15
16
17
20
19
13
9
11
12
Out
In
In
In
Out
In
In
In
Out
Table 1. Pin descriptions
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Hynix semiconductor
Specifications of HMS91C7432
1
WR
Strobe
Wait
Data[7:0]
Valid data
2
3
4
5
6
Figure 1. Data Write Cycle waveform
Data Write cycle phase transitions:
1. The Write line is asserted and the data is output to the parallel port
2. The data strobe is asserted, since WAIT is asserted low
3. The port waits for the acknowledge from the HMS91C7432 (WAIT de-asserted)
4. The data strobe is de-asserted
5. The write cycle ends
6. WAIT is asserted low to indicate that the next cycle may begin
1
WR
Strobe
Wait
Data[7:0]
2
3
4
5
Valid data
Figure 2. Data Read Cycle waveform
Data Read cycle phase transitions:
1. The Write line is set to HIGH to indicate read request
2. The data strobe is asserted, since WAIT is asserted low
3. The port waits for the acknowledge from the HMS91C7432 (WAIT de-asserted)
4. The data strobe is de-asserted after data is stored and the read cycle ends
5. WAIT is asserted low to indicate that the next cycle may begin
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