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ASM3P2107A-08-TT

Description
Peak EMI Reducing Solution
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size324KB,7 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Download Datasheet Parametric Compare View All

ASM3P2107A-08-TT Overview

Peak EMI Reducing Solution

ASM3P2107A-08-TT Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeSOIC
package instructionTSSOP,
Contacts8
Reach Compliance Codeunknow
ECCN codeEAR99
JESD-30 codeR-PDSO-G8
JESD-609 codee0
length4.4 mm
Number of terminals8
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency22 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Master clock/crystal nominal frequency22 MHz
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER
July 2005
rev 0.3
Peak EMI Reducing Solution
Features
FCC approved method of EMI attenuation.
Generates a 1X low EMI spread spectrum clock of
the input frequency.
Input frequency range: 12MHz to 22MHz.
Internal loop filter minimizes external components
and board space.
Frequency deviation: - 0.8%( Typ) @20MHz.
Low cycle-to-cycle jitter.
5.0V ± 5% operating voltage range.
TTL or CMOS compatible outputs.
Available in 8-pin SOIC and TSSOP Packages.
ASM3P2107A
savings by reducing the number of circuit board layers
ferrite beads, shielding and other passive components
that are traditionally required to pass EMI regulations.
The ASM3P2107A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.
The ASM3P2107A modulates the output of a single PLL
in order to “spread” the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
Product Description
The ASM3P2107A is a versatile spread spectrum
frequency modulator designed specifically for input clock
frequencies from 12MHz to 22MHz. The ASM3P2107A
can generate an EMI reduced clock from crystal, ceramic
resonator, or system clock.
The ASM3P2107A reduces electromagnetic interference
(EMI) at the clock source, allowing system wide reduction
of EMI of
down stream clock and data dependent
signals. The ASM3P2107A allows significant system cost
Applications
The ASM3P2107A is targeted towards EMI management
for high speed digital applications such as PC peripheral
devices, consumer electronics and embedded controller
systems.
Block Diagram
V
DD
Modulation
XIN
XOUT
Crystal
Oscillator
Frequency
Divider
Feedback
Divider
Phase
Detector
Loop
Filter
PLL
VCO
Output
Divider
CLOCKOUT
GND
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.

ASM3P2107A-08-TT Related Products

ASM3P2107A-08-TT ASM3P2107A ASM3P2107A-08-TR ASM3P2107AF-08-TR ASM3P2107AG-08-SR ASM3P2107AG-08-ST ASM3P2107AG-08-TT ASM3P2107AG-08-TR
Description Peak EMI Reducing Solution Peak EMI Reducing Solution Peak EMI Reducing Solution Peak EMI Reducing Solution Peak EMI Reducing Solution Peak EMI Reducing Solution Peak EMI Reducing Solution Peak EMI Reducing Solution
Is it Rohs certified? incompatible - incompatible conform to conform to conform to conform to conform to
Maker ALSC [Alliance Semiconductor Corporation] - ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation]
Parts packaging code SOIC - SOIC SOIC SOIC SOIC SOIC SOIC
package instruction TSSOP, - TSSOP, TSSOP, SOP, SOP, TSSOP, TSSOP,
Contacts 8 - 8 8 8 8 8 8
Reach Compliance Code unknow - unknow unknow unknow unknow unknow unknow
ECCN code EAR99 - EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
JESD-30 code R-PDSO-G8 - R-PDSO-G8 R-PDSO-G8 R-PDSO-G8 R-PDSO-G8 R-PDSO-G8 R-PDSO-G8
JESD-609 code e0 - e0 e3 e3 e3 e3 e3
length 4.4 mm - 4.4 mm 4.4 mm 4.9 mm 4.9 mm 4.4 mm 4.4 mm
Number of terminals 8 - 8 8 8 8 8 8
Maximum operating temperature 70 °C - 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
Maximum output clock frequency 22 MHz - 22 MHz 22 MHz 22 MHz 22 MHz 22 MHz 22 MHz
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP - TSSOP TSSOP SOP SOP TSSOP TSSOP
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH - SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) NOT SPECIFIED - NOT SPECIFIED 250 250 250 250 250
Master clock/crystal nominal frequency 22 MHz - 22 MHz 22 MHz 22 MHz 22 MHz 22 MHz 22 MHz
Certification status Not Qualified - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.1 mm - 1.1 mm 1.1 mm 1.75 mm 1.75 mm 1.1 mm 1.1 mm
Maximum supply voltage 5.25 V - 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V
Minimum supply voltage 4.75 V - 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V
Nominal supply voltage 5 V - 5 V 5 V 5 V 5 V 5 V 5 V
surface mount YES - YES YES YES YES YES YES
technology CMOS - CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL - COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface TIN LEAD - TIN LEAD Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn)
Terminal form GULL WING - GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm - 0.65 mm 0.65 mm 1.27 mm 1.27 mm 0.65 mm 0.65 mm
Terminal location DUAL - DUAL DUAL DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED 40 40 40 40 40
width 3 mm - 3 mm 3 mm 3.91 mm 3.91 mm 3 mm 3 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, OTHER - CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER

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