DATA SHEET
µ
PD77113A, 77114
16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS
MOS INTEGRATED CIRCUIT
DESCRIPTION
The
µ
PD77113A and 77114 are 16-bit fixed-point digital signal processors (DSPs).
Compared with the
µ
PD77016 family, these DSPs have improved power consumption and are ideal for battery-
powered mobile terminals such as PDAs and cellular phones.
Both mask ROM and RAM models are available.
For details of the functions of these DSPs, refer to the following User’s Manuals:
µ
PD77111 Family User’s Manual
: U14623E
µ
PD77016 Family User’s Manual - Instructions : U13116E
FEATURES
z
Instruction cycle (operating clock)
µ
PD77113A : 13.3 ns MIN (75 MHz MAX)
µ
PD77114 : 13.3 ns MIN (75 MHz MAX)
z
Memory
• Internal instruction memory
µ
PD77113A : RAM 3.5K words
×
32 bits
Mask ROM 48K words
×
32 bits
µ
PD77114 : RAM 3.5K words
×
32 bits
Mask ROM 48K words
×
32 bits
• Data memory
µ
PD77113A : RAM 16K words
×
16 bits
×
2 banks
Mask ROM 32K words
×
16 bits
×
2 banks
µ
PD77114 : RAM 16K words
×
16 bits
×
2 banks
Mask ROM 32K words
×
16 bits
×
2 banks
External memory space 8K words
×
16 bits
×
2 banks
ORDERING INFORMATION
Part Number
Package
80-pin plastic fine-pitch BGA (9
×
9)
100-pin plastic TQFP (fine pitch) (14
×
14)
µ
PD77113AF1-xxx-CN1
µ
PD77114GC-xxx-9EU
Remark
xxx indicates ROM code suffix.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14373EJ3V0DS00 (3rd edition)
Date Published February 2001 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1999
4
µ
PD77018A
256
×
32
24K
×
32
None
24K
×
16 each
3K
×
16 each
3K
×
16 each
31.75K
×
32
48K
×
32
16K
×
16 each
4K
×
32
35.5K
×
32
1K
×
32
3.5K
×
32
DSP FUNCTION LIST
µ
PD77019
µ
PD77019-013
µ
PD77110
µ
PD77111
µ
PD77112
µ
PD77113A
µ
PD77114
Item
µ
PD77016
1.5K
×
32
Memory space Internal instruction RAM
(words
×
bits)
Internal instruction ROM
None
Data RAM
(X/Y memory)
12K
×
16 each
None
16K
×
16 each
2K
×
16 each
Data ROM
(X/Y memory)
None
None
32K
×
16 each
External instruction
memory
16K
×
16 each
None
32K
×
16 each
48K
×
32
External data memory
48K
×
16 each
16K
×
16 each
None
8K
×
16 each
(X/Y memory)
16.6 ns (60 MHz)
15.3 ns (65 MHz)
Fixed to
×4
Integer of
×1
to 8
(external pin)
×1,
2, 3, 4, 8 (mask option)
13.3 ns (75 MHz)
Integer of
×1
to 16 (mask option)
Instruction cycle (at maximum speed)
–
30 ns (33 MHz)
Data Sheet U14373EJ3V0DS
Multiple
Serial interface (two channels)
Channels 1 and 2 Channel 1 has same function as
µ
PD77016. Channel 2 does not have SORQ2 and SIAK2 pins (for connection of codec).
have same function.
5V
3V
DSP core: 2.5 V
I/O pins : 3 V
100-pin TQFP
80-pin TQFP
80-pin FBGA
100-pin TQFP
80-pin FBGA
100-pin TQFP
Supply voltage
Package
116-pin BGA
160-pin QFP
100-pin TQFP
µ
PD77113A, 77114
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