July 2005
rev 1.0
ASM3P623S00A/B/C/D/E/F
Zero Cycle Slip Peak EMI reduction IC
General Features
Input frequency range: 20MHz - 50MHz.
Zero input - output propagation delay.
Low-skew outputs.
Output-output skew less than 250pS.
Device-device skew less than 700pS.
Less than 200pS cycle-to-cycle jitter is compatible
with Pentium
®
based systems.
Available in 16pin, 150mil SOIC, 4.4mm TSSOP
(ASM3P623S00D/E/F), and in 8pin, 150 mil SOIC,
4.4mm TSSOP Packages (ASM3P623S00A/B/C).
3.3V operation
Advanced 0.35µ CMOS technology.
The First True Drop-in Solution.
All parts have on-chip PLLs that lock to an input clock on
the CLKIN pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad, internal to the device.
Multiple ASM3P623S00D/E/F devices can accept the same
input clock and distribute it. In this case, the skew between
the outputs of the two devices is guaranteed to be less than
700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 250pS, and the output-to-output skew is
guaranteed to be less than 250pS.
Please refer
“
Differential Cycle Slips and Spread Spectrum
Control Table” for deviations and differential Cycle Slips
for ASM3P623S00A/B/C and the ASM3P623S00D/E/F
devices
Functional Description
ASM3P623S00D/E/F is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks. It accepts one
reference input and drives out eight low-skew clocks. It is
available in a 16pin package. The ASM3P623S00A/B/C is
the eight-pin version of the ASM3P623S00. It accepts one
reference input and drives out one low-skew clock.
The ASM3P623S00A/B/C and the ASM3P623S00D/E/F
are available in two different configurations, as shown in
the ordering information table.
Block Diagram
V
DD
SSON
SS%
Modulation
Reference
Divider
Feedback
Divider
PLL
CLKIN
Phase
Detector
Loop
Filter
VCO
Feedforward
Divider
CLKOUT
V
SS
Alliance Semiconductor
2575 Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
July 2005
rev 1.0
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the
edge rates also get faster. Analysis shows that a square
wave is composed of fundamental frequency and
harmonics. The fundamental frequency and harmonics
generate the energy peaks that become the source of
EMI. Regulatory agencies test electronic equipment by
measuring the amount of peak energy radiated from the
equipment. In fact, the peak level allowed decreases as
the frequency increases. The standard methods of
reducing EMI are to use shielding, filtering, multi-layer
ASM3P623S00A/B/C/D/E/F
PCBs etc. These methods are expensive. Spread
spectrum clocking reduces the peak energy by reducing
the Q factor of the clock. This is done by slowly
modulating the clock frequency. The ASM3P623S00X
uses the center modulation spread spectrum technique in
which the modulated output frequency varies above and
below
the
reference
frequency
with
a
specified
modulation rate. With center modulation, the average
frequency is the same as the unmodulated frequency and
there is no performance degradation
Cycle Slip
Cycle slip occurs when the output clock edge
‘wanders’ away from the corresponding input clock
edge. There are two types of cycle slips – a Differential
cycle slip and an Integral cycle slip. The differential
cycle slip is caused due the clock edge variation over
one modulation cycle. It is defined by the maximum
amount of ‘wander’ the clock edge will have within one
modulation cycle. Integral cycle slip occurs due to the
accumulation of the cycle slip over successive modulation
cycles. In ASM3P623S00A/B/C/D/E/F the differential cycle
slip is within the value mentioned in the
“
Differential Cycle
Slip and Spread Spectrum Control Table” and the Integral
Cycle Slip is ‘Zero’.
Pin Configuration
CLKIN
NC
SS%
GND
1
2
3
4
8
NC
V
DD
CLKOUT
SSON
ASM3P623S00A/B/C
7
6
5
CLKIN
CLKOUT1
VDD
SS%
GND
CLKOUT2
CLKOUT3
DLY CNTRL
1
2
3
4
5
6
7
8
16
15
14
CLKOUT8
CLKOUT7
CLKOUT6
VDD
GND
CLKOUT5
CLKOUT4
SSON
ASM3P623S00 D/E/F
13
12
11
10
9
Zero Cycle Slip Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 16
July 2005
rev 1.0
Pin Description for ASM3P623S00A/B/C
Pin #
1
2
3
4
5
6
7
8
Pin Name
CLKIN
2
NC
SS%
4
GND
SSON
4
CLKOUT
1,3
VDD
NC
No Connect
Spread Spectrum Selection
Ground
ASM3P623S00A/B/C/D/E/F
Description
Input reference frequency, 5V-tolerant input
Spread Spectrum enable and disable option When SSON is HIGH, the spread
spectrum is enabled and when LOW, it turns off the spread spectrum.
Buffered clock output
3.3V supply
No Connect
Pin Description for ASM3P623S00D/E/F
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
CLKIN
2
CLKOUT1
3
VDD
SS%
4
GND
CLKOUT2
3
CLKOUT3
3
DLY CNTRL
SSON
4
CLKOUT4
3
CLKOUT5
3
GND
VDD
CLKOUT6
3
CLKOUT7
3
CLKOUT8
3
Description
Input reference frequency, 5V tolerant input
Buffered clock output
3.3V supply
Spread Spectrum Selection
Ground
Buffered clock output
Buffered clock output
The pin is used to skew the outputs such that they align with the input. The skew can
is in the range of 100-200pS
Spread Spectrum enable and disable option. When SSON is HIGH, the spread
spectrum is enabled and when LOW, it turns off the spread spectrum.
Buffered clock output
Buffered clock output
Ground
3.3V supply
Buffered clock output
Buffered clock output
Buffered clock output
Notes:
1. This output is driven and has an internal feedback for the PLL.
2. Weak pull-down. 3. Weak pull-down on all outputs. 4. Weak pull-up on these inputs.
Zero Cycle Slip Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 16
July 2005
rev 1.0
Differential Cycle Slips and Spread Spectrum Control Table
(Note: The values given in the table are for an input frequency of 32 MHz)
ASM3P623S00A/B/C/D/E/F
Device
ASM3P623S00A
SS%
0
1
0
1
0
1
0
1
0
1
0
1
Deviation
±0.5 %
±1 %
±0.25 %
±0.5 %
±0.125 %
±0.25 %
±0.5 %
±1 %
±0.25 %
±0.5 %
±0.125 %
±0.25 %
Differential Cycle Slips
(Nd)
0.125
0.25
0.125
0.25
0.125
0.25
0.125
0.25
0.125
0.25
0.125
0.25
ASM3P623S00B
ASM3P623S00C
ASM3P623S00D
ASM3P623S00E
ASM3P623S00F
Absolute Maximum Ratings
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except CLKIN)
DC Input Voltage (CLKIN)
Storage Temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Min
-0.5
-0.5
-0.5
-65
Max
+7.0
VDD + 0.5
7
+150
260
150
2000
Unit
V
V
V
°C
°C
°C
V
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device
reliability.
Zero Cycle Slip Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 16
July 2005
rev 1.0
ASM3P623S00A/B/C/D/E/F
Operating Conditions for ASM3P623S00A/B/C and ASM3P623S00D/E/F Devices
Parameter
VDD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Description
Min
3.0
0
Max
3.6
70
30
7
Unit
V
°C
pF
pF
Electrical Characteristics for ASM3P623S00A/B/C and ASM3P623S00D/E/F
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Z
o
Description
Input LOW Voltage
5
Input HIGH Voltage
5
Input LOW Current
Input HIGH Current
Output LOW Voltage
6
Output HIGH Voltage
Supply Current
Output Impedance
6
Test Conditions
Min
2.0
Typ
Max
0.8
Unit
V
V
µA
µA
V
V
mA
Ω
V
IN
= 0V
V
IN
= VDD
I
OL
= 8mA
I
OH
= -8mA
Unloaded outputs
2.4
15
23
50
100
0.4
Switching Characteristics for ASM3P623S00A/B/C and ASM3P623S00D/E/F
7
Parameter
1/t
1
t
3
t
4
t
5
t
6
t
7
t
J
t
LOCK
Notes:
5. CLKIN input has a threshold voltage of VDD/2
6. Parameter is guaranteed by design and characterization. Not 100% tested in production
7. All parameters specified with loaded outputs.
Description
Output Frequency
Duty Cycle
6
= (t
2
/ t
1
) * 100
Output Rise Time
6
Output Fall Time
6
Output-to-output skew
6
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge
6
Test Conditions
30pF load
Measured at VDD/2
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
Measured at VDD /2
Measured at VDD/2 on the CLKOUT pins
of the device
Loaded outputs
Stable power supply, valid clock presented
on CLKIN pin
Min
20
40
Typ
50
Max
50
60
2.5
2.5
250
±350
700
200
1.0
Unit
MHz
%
nS
nS
pS
pS
pS
pS
mS
Device-to-Device Skew
6
Cycle-to-cycle jitter
6
PLL Lock Time
6
Zero Cycle Slip Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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