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LTC2232UK

Description
10-Bit,105Msps/80Msps ADCs
File Size812KB,28 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
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LTC2232UK Overview

10-Bit,105Msps/80Msps ADCs

LTC2232/LTC2233
10-Bit,105Msps/
80Msps ADCs
FEATURES
DESCRIPTIO
Sample Rate: 105Msps/80Msps
61dB SNR up to 140MHz Input
75dB SFDR up to 200MHz Input
775MHz Full Power Bandwidth S/H
Single 3.3V Supply
Low Power Dissipation: 475mW/366mW
Selectable Input Ranges:
±0.5V
or
±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)
48-Pin 7mm x 7mm QFN Package
The LTC
®
2232 and LTC2233 are 105Msps/80Msps, sam-
pling 10-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2232/
LTC2233 are perfect for demanding communications
applications with AC performance that includes 61dB SNR
and 75dB spurious free dynamic range for signals
up to 200MHz. Ultralow jitter of 0.15ps
RMS
allows
undersampling of IF frequencies with excellent noise
performance.
DC specs include
±0.15LSB
INL (typ),
±0.1LSB
DNL (typ)
and
±0.8LSB
INL,
±0.6LSB
DNL over temperature. The
transition noise is a low 0.12LSB
RMS
.
A separate output power supply allows the outputs to drive
0.5V to 3.6V logic.
The ENC
+
and ENC
inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
APPLICATIO S
Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
TYPICAL APPLICATIO
REFH
REFL
3.3V
V
DD
FLEXIBLE
REFERENCE
0.5V
TO 3.6V
OV
DD
ANALOG
INPUT
INPUT
S/H
10-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
SFDR (dBFS)
+
D9
D0
OGND
CLOCK/DUTY
CYCLE
CONTROL
22323 TA01
ENCODE INPUT
U
SFDR vs Input Frequency
90
85
4th OR HIGHER
80
75
70
2nd OR 3rd
65
60
55
50
0
100
200
300
400
500
600
22323 TA01b
INPUT FREQUENCY (MHz)
22323fa
U
U
1

LTC2232UK Related Products

LTC2232UK LTC2232CUK LTC2232IUK LTC2233CUK LTC2233IUK LTC2233UK
Description 10-Bit,105Msps/80Msps ADCs 10-Bit,105Msps/80Msps ADCs 10-Bit,105Msps/80Msps ADCs 10-Bit,105Msps/80Msps ADCs 10-Bit,105Msps/80Msps ADCs 10-Bit,105Msps/80Msps ADCs
Brand Name - Linear Technology Linear Technology Linear Technology Linear Technology -
Is it Rohs certified? - incompatible incompatible incompatible incompatible -
Maker - Linear ( ADI ) Linear ( ADI ) Linear ( ADI ) Linear ( ADI ) -
Parts packaging code - QFN QFN QFN QFN -
package instruction - HVQCCN, LCC48,.27SQ,20 HVQCCN, LCC48,.27SQ,20 HVQCCN, LCC48,.27SQ,20 HVQCCN, LCC48,.27SQ,20 -
Contacts - 48 48 48 48 -
Manufacturer packaging code - UK UK UK UK -
Reach Compliance Code - _compli _compli _compli _compli -
ECCN code - 3A991.C.1 3A991.C.1 EAR99 EAR99 -
Maximum analog input voltage - 1 V 1 V 1 V 1 V -
Minimum analog input voltage - -1 V -1 V -1 V -1 V -
Converter type - ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD -
JESD-30 code - S-PQCC-N48 S-PQCC-N48 S-PQCC-N48 S-PQCC-N48 -
JESD-609 code - e0 e0 e0 e0 -
length - 7 mm 7 mm 7 mm 7 mm -
Maximum linear error (EL) - 0.0781% 0.0781% 0.0781% 0.0781% -
Humidity sensitivity level - 1 1 1 1 -
Number of analog input channels - 1 1 1 1 -
Number of digits - 10 10 10 10 -
Number of functions - 1 1 1 1 -
Number of terminals - 48 48 48 48 -
Maximum operating temperature - 70 °C 85 °C 70 °C 85 °C -
Output bit code - OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY -
Output format - PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD -
Package body material - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY -
encapsulated code - HVQCCN HVQCCN HVQCCN HVQCCN -
Encapsulate equivalent code - LCC48,.27SQ,20 LCC48,.27SQ,20 LCC48,.27SQ,20 LCC48,.27SQ,20 -
Package shape - SQUARE SQUARE SQUARE SQUARE -
Package form - CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE -
Peak Reflow Temperature (Celsius) - 235 235 235 235 -
power supply - 3.3 V 3.3 V 3.3 V 3.3 V -
Certification status - Not Qualified Not Qualified Not Qualified Not Qualified -
Sampling rate - 105 MHz 105 MHz 80 MHz 80 MHz -
Sample and hold/Track and hold - SAMPLE SAMPLE SAMPLE SAMPLE -
Maximum seat height - 0.8 mm 0.8 mm 0.8 mm 0.8 mm -
Nominal supply voltage - 3.3 V 3.3 V 3.3 V 3.3 V -
surface mount - YES YES YES YES -
technology - CMOS CMOS CMOS CMOS -
Temperature level - COMMERCIAL INDUSTRIAL COMMERCIAL INDUSTRIAL -
Terminal surface - Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) -
Terminal form - NO LEAD NO LEAD NO LEAD NO LEAD -
Terminal pitch - 0.5 mm 0.5 mm 0.5 mm 0.5 mm -
Terminal location - QUAD QUAD QUAD QUAD -
Maximum time at peak reflow temperature - 20 20 20 20 -
width - 7 mm 7 mm 7 mm 7 mm -
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