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LTC2204

Description
1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
Categorysemiconductor    logic   
File Size2MB,36 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
Download Datasheet Parametric View All

LTC2204 Overview

1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48

LTC2204 Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals48
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Rated supply voltage3.3 V
Maximum linear error0.0069 %
Maximum limit analog input voltage1.5 V
Minimum limit analog input voltage1 V
Processing package description7 X 7 MM, PLASTIC, MO-220WKKD-2, QFN-48
stateACTIVE
CraftsmanshipCMOS
packaging shapeSQUARE
Package SizeCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
surface mountYes
Terminal formNO LEAD
Terminal spacing0.5000 mm
terminal coatingTIN LEAD
Terminal locationQUAD
Packaging MaterialsPLASTIC/EPOXY
Temperature levelINDUSTRIAL
Sampling Rate65 MHz
Output formatPARALLEL, WORD
Type of converterPROPRIETARY METHOD
Number of digits16
Output bit encodingOFFSET BINARY, 2S COMPLEMENT BINARY
Number of analog channels1
Sample and hold and track and holdSAMPLE
FEATURES
n
n
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n
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LTC2205/LTC2204
16-Bit, 65Msps/40Msps
ADCs
DESCRIPTIO
The LTC
®
2205/LTC2204 are sampling 16-bit A/D converters
designed for digitizing high frequency, wide dynamic range
signals up to input frequencies of 700MHz. The input range
of the ADC can be optimized with the PGA front end.
The LTC2205/LTC2204 are perfect for demanding com-
munications applications, with AC performance that in-
cludes 79dB SNR and 100dB spurious free dynamic range
(SFDR). Ultralow jitter of 90fs
RMS
allows undersampling of
high input frequencies with excellent noise performance.
Maximum DC specs include ±4LSB INL, ±1LSB DNL (no
missing codes).
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC
+
and ENC
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
n
Sample Rate: 65Msps/40Msps
79dB SNR and 100dB SFDR (2.25V
P-P
Range)
SFDR >92dB at 140MHz (1.5V
P-P
Input Range)
PGA Front End (2.25V
P-P
or 1.5V
P-P
Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
Single 3.3V Supply
Power Dissipation: 610mW/480mW
Optional Clock Duty Cycle Stabilizer
Out-of-Range Indicator
Pin Compatible Family
105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit)
80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit)
65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit)
40Msps: LTC2204 (16-Bit)
48-Pin (7mm
×
7mm) QFN Package
APPLICATIO S
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Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
TYPICAL APPLICATIO
3.3V
SENSE
V
CM
2.2µF
1.25V
COMMON MODE
BIAS VOLTAGE
INTERNAL ADC
REFERENCE
GENERATOR
OV
DD
0.5V TO 3.6V
0.1µF
OF
CLKOUT
D15
D0
0
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–140
0
AIN
+
ANALOG
INPUT
AIN
+
S/H
AMP
16-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
OGND
CLOCK/DUTY
CYCLE
CONTROL
V
DD
GND
ENC
ENC
PGA
SHDN
DITH
MODE
OE
RAND
0.1µF
0.1µF
3.3V
0.1µF
22076 TA01
ADC CONTROL INPUTS
U
U
U
LTC2205: 64K Point FFT,
f
IN
= 5.1MHz, –1dBFS,
PGA = 0, DITH = 0
5
20
15
25
10
FREQUENCY (MHz)
30
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