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LTC2222UK-11

Description
11-Bit, 105Msps ADC
File Size556KB,24 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
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LTC2222UK-11 Overview

11-Bit, 105Msps ADC

LTC2222-11
11-Bit, 105Msps ADC
FEATURES
DESCRIPTIO
Sample Rate: 105Msps
65.4dB SNR up to 140MHz Input
80dB SFDR up to 150MHz Input
775MHz Full Power Bandwidth S/H
Single 3.3V Supply
Low Power Dissipation: 475mW
CMOS Outputs
Selectable Input Ranges:
±0.5V
or
±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)
48-Pin 7mm
×
7mm QFN Package
The LTC
®
2222-11 is a 105Msps, sampling 11-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2222-11 is perfect for
demanding communications applications with AC perfor-
mance that includes 65.4dB SNR and 80dB spurious free
dynamic range for signals up to 150MHz. Ultralow jitter of
0.15ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include
±0.15LSB
INL (typ),
±0.1LSB
DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.25LSB
RMS
.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.3V.
The ENC
+
and ENC
inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
APPLICATIO S
Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
3.3V
V
DD
0.5V TO 3.3V
OV
DD
95
90
4th OR HIGHER
85
SFDR (dBFS)
80
75
70
65
2nd OR 3rd
+
ANALOG
INPUT
INPUT
S/H
11-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
D10
D0
OGND
CLOCK/DUTY
CYCLE
CONTROL
222211 TA01
60
55
50
0
100
200
300
400
500
INPUT FREQUENCY (MHz)
600
ENCODE
INPUT
U
SFDR vs Input Frequency
222211 TA01b
U
U
222211f
1

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