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LTC2224CUK

Description
1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
CategoryAnalog mixed-signal IC    converter   
File Size580KB,24 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
Download Datasheet Parametric Compare View All

LTC2224CUK Overview

1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48

LTC2224CUK Parametric

Parameter NameAttribute value
Brand NameLinear Technology
Is it Rohs certified?incompatible
MakerLinear ( ADI )
Parts packaging codeQFN
package instructionHVQCCN, LCC48,.27SQ,20
Contacts48
Manufacturer packaging codeUK
Reach Compliance Code_compli
ECCN code3A991.C.2
Maximum analog input voltage1 V
Minimum analog input voltage-1 V
Converter typeADC, PROPRIETARY METHOD
JESD-30 codeS-PQCC-N48
JESD-609 codee0
length7 mm
Maximum linear error (EL)0.0244%
Humidity sensitivity level1
Number of analog input channels1
Number of digits12
Number of functions1
Number of terminals48
Maximum operating temperature70 °C
Minimum operating temperature
Output bit codeOFFSET BINARY, 2\'S COMPLEMENT BINARY
Output formatPARALLEL, WORD
Package body materialPLASTIC/EPOXY
encapsulated codeHVQCCN
Encapsulate equivalent codeLCC48,.27SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)235
power supply3.3 V
Certification statusNot Qualified
Sampling rate135 MHz
Sample and hold/Track and holdSAMPLE
Maximum seat height0.8 mm
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width7 mm
LTC2224
12-Bit, 135Msps ADC
FEATURES
DESCRIPTIO
Sample Rate: 135Msps
67.3dB SNR up to 140MHz Input
80dB SFDR up to 150MHz Input
775MHz Full Power Bandwidth S/H
Single 3.3V Supply
Low Power Dissipation: 630mW
CMOS Outputs
Selectable Input Ranges:
±0.5V
or
±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)
48-Pin 7mm
×
7mm QFN Package
The LTC
®
2224 is a 135Msps, sampling 12-bit A/D con-
verter designed for digitizing high frequency, wide dy-
namic range signals. The LTC2224 is perfect for demand-
ing communications applications with AC performance
that includes 67.3dB SNR and 80dB spurious free dy-
namic range for signals up to 150MHz. Ultralow jitter of
0.15ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include
±0.4LSB
INL (typ),
±0.3LSB
DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.5LSB
RMS
.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC
+
and ENC
inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
APPLICATIO S
Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
3.3V
V
DD
0.5V TO 3.6V
OV
DD
+
ANALOG
INPUT
INPUT
S/H
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
D11
D0
SFDR (dBFS)
OGND
CLOCK/DUTY
CYCLE
CONTROL
2224 TA01
ENCODE
INPUT
U
SFDR vs Input Frequency
95
90
4th OR HIGHER
85
80
75
70
65
60
55
50
0
100
400
500
INPUT FREQUENCY (MHz)
200
300
600
2nd OR 3rd
2224 TA01b
U
U
2224fa
1

LTC2224CUK Related Products

LTC2224CUK LTC2224IUK LTC2224UK
Description 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
Number of digits 12 12 12
Number of functions 1 1 1
Number of terminals 48 48 48
Maximum operating temperature 70 °C 85 °C 70 Cel
Minimum operating temperature - -40 °C 0.0 Cel
Output format PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD
surface mount YES YES Yes
Temperature level COMMERCIAL INDUSTRIAL COMMERCIAL
Terminal form NO LEAD NO LEAD NO LEAD
Terminal location QUAD QUAD QUAD
Brand Name Linear Technology Linear Technology -
Is it Rohs certified? incompatible incompatible -
Maker Linear ( ADI ) Linear ( ADI ) -
Parts packaging code QFN QFN -
package instruction HVQCCN, LCC48,.27SQ,20 HVQCCN, LCC48,.27SQ,20 -
Contacts 48 48 -
Manufacturer packaging code UK UK -
Reach Compliance Code _compli _compli -
ECCN code 3A991.C.2 3A991.C.2 -
Maximum analog input voltage 1 V 1 V -
Minimum analog input voltage -1 V -1 V -
Converter type ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD -
JESD-30 code S-PQCC-N48 S-PQCC-N48 -
JESD-609 code e0 e0 -
length 7 mm 7 mm -
Maximum linear error (EL) 0.0244% 0.0244% -
Humidity sensitivity level 1 1 -
Number of analog input channels 1 1 -
Output bit code OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY -
Package body material PLASTIC/EPOXY PLASTIC/EPOXY -
encapsulated code HVQCCN HVQCCN -
Encapsulate equivalent code LCC48,.27SQ,20 LCC48,.27SQ,20 -
Package shape SQUARE SQUARE -
Package form CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE -
Peak Reflow Temperature (Celsius) 235 235 -
power supply 3.3 V 3.3 V -
Certification status Not Qualified Not Qualified -
Sampling rate 135 MHz 135 MHz -
Sample and hold/Track and hold SAMPLE SAMPLE -
Maximum seat height 0.8 mm 0.8 mm -
Nominal supply voltage 3.3 V 3.3 V -
technology CMOS CMOS -
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) -
Terminal pitch 0.5 mm 0.5 mm -
Maximum time at peak reflow temperature 20 20 -
width 7 mm 7 mm -
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