Less than 200 pS cycle-to-cycle jitter is compatible
with Pentium based systems.
Test Mode to bypass PLL (ASM5P23S09A only,
refer Select Input Decoding Table).
Available in 16-pin, 150-mil SOIC and 4.4 mm
TSSOP packages for ASM5P23S09A and in
8-pin, 150-mil SOIC and 4.4 mm TSSOP
packages for ASM5P23S05A.
3.3V operation
Advanced 0.35< CMOS technology.
‘SpreadTrak’.
®
ASM5P23S09A
ASM5P23S05A
out five low-skew clocks.
The -1H version of the ASM5P23SxxA operates at up to
133 MHz frequency, and has higher drive than the -1
device. All parts have on-chip PLLs that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
The ASM5P23S09A has two banks of four outputs each,
which can be controlled by the Select inputs as shown in
the Select Input Decoding Table. If all the output clocks are
not required, Bank B can be three-stated. The select input
also allows the input clock to be directly applied to the
outputs for chip and system testing purposes.
Multiple ASM5P23S09A and ASM5P23S05A devices can
accept the same input clock and distribute it. In this case
the skew between the outputs of the two devices is
guaranteed to be less than 700 pS.
All outputs have less than 200 pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 250 pS, and the output to output skew is
guaranteed to be less than 250 pS.
The ASM5P23S09A and the ASM5P23S05A are available
in two different configurations, as shown in the ordering
information table. The ASM5P23SxxA-1 is the base part.
The ASM5P23SxxA-1H is the high drive version of the -1
part and its rise and fall times are much faster than -1 part.
Functional Description
ASM5P23S09A is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks with Spread
Spectrum capability. It is available in a 16-pin package. The
ASM5P23S05A
is
the
eight-pin
version
of
the
ASM5P23S09A. It accepts one reference input and drives
Block Diagram
REF
PLL
CLKOUT
CLK1
CLK2
CLK3
CLK4
PLL
REF
MUX
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
S2
Select Input
Decoding
CLKB1
CLKB2
CLKB3
CLKB4
S1
ASM5P23S05A
ASM5P23S09A
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
November 2004
rev 1.3
Select Input Decoding for ASM5P23S09A
1
ASM5P23S09A
ASM5P23S05A
S2
0
0
1
1
Note:
S1
0
1
0
1
Clock A1 - A4
Three-state
Driven
Driven
Driven
Clock B1 - B4
Three-state
Three-state
Driven
Driven
CLKOUT
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL
Shut-Down
N
N
Y
N
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the
output.
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input-output delay.
For applications requiring zero input-output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero-input-output
delay.
SpreadTrak
Many systems being designed now utilize a technology
called Spread Spectrum Frequency Timing Generation.
ASM5P23S09A and ASM5P23S05A are designed so as
not to filter off the Spread Spectrum feature of the
Reference input, assuming it exists. When a zero delay
buffer is not designed to pass the Spread Spectrum feature
through, the result is a significant amount of tracking skew
which may cause problems in the systems requiring
synchronization.
3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
2 of 18
November 2004
rev 1.3
Pin Configuration
ASM5P23S09A
ASM5P23S05A
REF
CLKA1
CLKA2
V
DD
1
2
3
4
5
6
7
8
16
15
14
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB1
CLKB2
S2
ASM5P23S09A
13
12
11
10
9
GND
CLKB4
CLKB3
S1
REF
CLK2
CLK1
GND
1
2
3
4
8
CLKOUT
CLK4
V
DD
ASM5P23S05A
7
6
5
CLK3
3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
3 of 18
November 2004
rev 1.3
Pin Description for ASM5P23S09A
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF
2
3
3
ASM5P23S09A
ASM5P23S05A
Description
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
Ground
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
S1
4
4
3
3
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
Select input, bit 1
CLKB3
CLKB4
GND
V
DD
CLKA3
CLKA4
3
3
Buffered clock output, bank B
Buffered clock output, bank B
Ground
3.3V supply
3
3
3
Buffered clock output, bank A
Buffered clock output, bank A
Buffered output, internal feedback on this pin
CLKOUT
Pin Description for ASM5P23S05A
Pin #
1
2
3
4
5
6
7
8
Pin Name
REF
2
3
3
Description
Input reference frequency, 5V-tolerant input
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V supply
Buffered clock output
CLK2
CLK1
CLK3
V
DD
CLK4
GND
3
3
3
CLKOUT
Buffered clock output, internal feedback on this pin
Notes:
2. Weak pull-down.
3. Weak pull-down on all outputs.
4. Weak pull-up on these inputs.
3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
4 of 18
November 2004
rev 1.3
Absolute Maximum Ratings
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(per MIL-STD-883, Method 3015)
Min
-0.5
-0.5
-0.5
-65
Max
+7.0
VDD + 0.5
7
+150
260
150
2000
ASM5P23S09A
ASM5P23S05A
Unit
V
V
V
°C
°C
°C
V
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device
reliability.
Operating Conditions for ASM5P23S05A and ASM5P23S09A - Commercial Temperature Devices
Parameter
V
DD
T
A
C
L
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
Description
Min
3.0
0
Max
3.6
70
30
10
7
Unit
V
°C
pF
pF
pF
Electrical Characteristics for ASM5P23S05A and ASM5P23S09A - Commercial Temperature Devices
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Z
O
Description
Input LOW Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
6
5
5
Test Conditions
Min
Typ
Max
0.8
Unit
V
V
<A
<A
V
V
Input HIGH Voltage
2.0
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8mA (-1)
I
OH
= 12mA (-1H)
I
OL
= -8mA (-1)
I
OH
= -12mA (-1H)
Unloaded outputs at
66.67 MHz, SEL inputs at V
DD
23
2.4
34
50.0
100.0
0.4
Output HIGH Voltage
Supply Current
Output Impedance
6
mA
K
Notes:
5. REF input has a threshold voltage of VDD/2
6. Parameter is guaranteed by design and characterization. Not 100% tested in production
3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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