2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer
Features
Output frequency range: 25MHz to 200MHz
Output frequency range: 16.67MHz to 200MHz
Input frequency range: 16.67MHz to 200MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
± 2% max Output duty cycle variation
11 Clock outputs: Drive up to 22 clock lines
LVCMOS reference clock input
125-pS max output-output skew
PLL bypass mode
Spread Aware
TM
ASM5I9352
The ASM5I9352 features an LVCMOS reference clock
input and provides 11 outputs partitioned in 3 banks of 5, 4,
and 2 outputs. Bank A divides the VCO output by 4 or 6
while Bank B divides by 4 and 2 and Bank C divides by 2
and 4 per SEL(A:C) settings, see Table 2. These dividers
allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and
1:3. Each LVCMOS compatible output can drive 50Ω series
or parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:22.
The PLL is ensured stable given that the VCO is configured
to run between 200 MHz to 500 MHz. This allows a wide
range of output frequencies from 16.67 MHz to 200 MHz.
For normal operation, the external feedback input, FB_IN,
is connected to one of the outputs. The internal VCO is
running at multiples of the input reference clock set by the
feedback divider, see Table 1.
Output enable/disable
Pin compatible with MPC9352 and MPC952
Industrial temperature range: –40°C to +85°C
32-Pin 1.0mm TQFP & LQFP Packages
Functional Description
The ASM5I9352 is a low voltage high performance
200MHz PLL-based zero delay buffer designed for high
speed clock distribution applications.
When PLL_EN# is HIGH, PLL is bypassed and the
reference clock directly feeds the output dividers. This
mode is fully static and the minimum input clock frequency
specification does not apply.
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.2
Block Diagram
ASM5I9352
PLL_EN#
REFCLK
FB_IN
VCO_SEL
SELA
Phase
Detector
VCO
200-500MHz
LPF
+2
+4/
+6
QA0
QA1
QA2
QA3
QA4
+4/
+2
QB0
QB1
QB2
QB3
SELB
+2/
+4
SELC
MR/OE#
QC0
QC1
Pin Configuration
VDDQC
QB3
VSS
VDDQB
QC1
QC0
QB2
VSS
32 31 30 29 28 27 26 25
VCO_SEL
SELC
SELB
SELA
MR/OE#
REFCLK
AVSS
FB_IN
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
24
23
22
VSS
QB1
QB0
VDDQB
VDDQA
QA4
QA3
VSS
ASM5I9352
21
20
19
18
17
PLL_EN#
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
VDDQA
AVDD
VDD
VSS
QA0
QA1
QA2
2 of 12
July 2005
rev 0.2
Pin Configuration
1
Pin
6
12, 14,
15, 18, 19
22, 23,
26, 27
30, 31
8
1
5
9
2, 3, 4
16, 20
21, 25
32
10
11
7
13, 17,
24, 28, 29
ASM5I9352
Name
REFCLK
QA(0:4)
QB(0:3)
QC(0,1)
FB_IN
VCO_SEL
MR/OE#
PLL_EN#
SEL(A:C)
V
DDQA
V
DDQB
V
DDQC
AV
DD
V
DD
AV
SS
V
SS
I/O
I, PD
O
O
O
I, PD
I, PD
I, PD
I, PD
I, PD
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
V
DD
V
DD
V
DD
V
DD
V
DD
Ground
Ground
Reference clock input.
Clock output bank A.
Clock output bank B.
Clock output bank C.
Description
Feedback clock input.
Connect to an output for normal operation.
This input should be at the same voltage rail as input reference
clock. See
Table 1.
VCO divider select input.
See
Table 2.
Master reset/output enable/disable input.
See
Table 2.
PLL enable/disable input.
See Table 2.
Frequency select input, Bank (A:C).
See
Table 2.
2.5V or 3.3V power supply for bank A output clocks
2,3
.
2.5V or 3.3V power supply for bank B output clocks.
2,3
2.5V or 3.3V power supply for bank C output clocks.
2,3
2.5V or 3.3V power supply for PLL.
2,3
2.5V or 3.3V power supply for core and inputs.
2,3
Analog ground.
Common ground.
Note: 1. PD = Internal pull-down.
2.A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins
their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3.AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output
supply pins.
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
3 of 12
July 2005
rev 0.2
Table 1: Frequency Table
VCO_SEL
0
0
0
1
1
1
ASM5I9352
Feedback
Output Divider
÷2
÷4
÷6
÷2
÷4
÷6
VCO
Input Clock * 2
Input Clock * 4
Input Clock * 6
Input Clock * 4
Input Clock * 8
Input Clock * 12
Input Frequency Range
(AVDD = 3.3V)
100 MHz to 200 MHz
50 MHz to 125 MHz
33.33 MHz to 83.33 MHz
50 MHz to 125 MHz
25 MHz to 62.5 MHz
16.67 MHz to 41.67 MHz
Input Frequency
Range (AVDD = 2.5V)
100 MHz to 200 MHz
50 MHz to 100 MHz
33.33 MHz to 66.67 MHz
50 MHz to 100 MHz
25 MHz to 50 MHz
16.67 MHz to 33.33 MHz
Table 2: Function Table
Control
VCO_SEL
PLL_EN#
MR/OE#
SELA
SELB
SELC
Default
0
0
0
0
0
0
0
VCO
PLL enabled. The VCO output
connects to the output dividers
Outputs enabled
QA = VCO÷4
QB = VCO ÷4
QC = VCO÷2
1
VCO ÷ 2
Bypass mode, PLL disabled. The input clock
connects to the output dividers
Outputs disabled (three-state), VCO running
at its minimum frequency
QA = VCO÷6
QB = VCO÷2
QC = VCO÷4
Absolute Maximum Ratings
Parameter
V
DD
V
DD
V
IN
V
OUT
V
TT
LU
R
PS
T
S
T
A
T
J
Ø
JC
Ø
JA
ESD
H
FIT
Description
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
DC Output Voltage
Output termination Voltage
Latch Up Immunity
Power Supply Ripple
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
Condition
Functional
Relative to V
SS
Relative to V
SS
Functional
Ripple Frequency < 100 kHz
Non Functional
Functional
Functional
Functional
Functional
Min
–0.3
2.375
–0.3
–0.3
200
Max
5.5
3.465
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
÷2
150
Unit
V
V
V
V
V
mA
mVp-p
°C
°C
°C
°C/W
°C/W
Volts
ppm
–65
–40
+150
+85
155
42
105
2000
Manufacturing test
10
Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for extended periods may affect device
reliability.
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
4 of 12
July 2005
rev 0.2
DC Electrical Specifications
(V
DD
= 2.5V ± 5%, T
A
= -40°C to +85°C)
Parameter
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
I
DDA
I
DDQ
I
DD
C
IN
Z
OUT
ASM5I9352
Description
Input Voltage, Low
Input Voltage, High
Output Voltage, Low
1
Output Voltage, High
1
Input Current, Low
Input Current, High
2
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
Condition
LVCMOS
LVCMOS
I
OL
= 15 mA
I
OH
= –15 mA
V
IL
= V
SS
V
IL
= V
DD
AV
DD
only
All V
DD
pins except AV
DD
Min
1.7
1.8
Typ
Max
0.7
V
DD
+ 0.3
0.6
–10
100
Unit
V
V
V
V
µA
µA
mA
mA
mA
pF
Ω
5
3
170
4
17 – 20
10
5
Note:1.Driving one 50Ω parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50
Ω
series terminated
transmission lines.
2.Inputs have pull-down resistors that affect the input current.
DC Electrical Specifications
(V
DD
= 3.3V ± 5%, T
A
= -40°C to +85°C)
Parameter
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
I
DDA
I
DDQ
I
DD
C
IN
Z
OUT
Description
Input Voltage, Low
Input Voltage, High
Output Voltage, Low
1
Output Voltage, High
1
Input Current, Low
Input Current, High
2
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
Condition
LVCMOS
LVCMOS
I
OL
= 24 mA
I
OL
= 12 mA
I
OH
= –24 mA
V
IL
= V
SS
V
IL
= V
DD
AV
DD
only
All V
DD
pins except AV
DD
Min
2.0
Typ
Max
0.8
V
DD
+ 0.3
0.55
0.30
Unit
V
V
V
V
2.4
–10
100
5
3
240
4
14 – 17
10
5
µA
µA
mA
mA
mA
pF
Ω
Note:1.Driving one 50Ω parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50
Ω
series terminated
transmission lines.
2.Inputs have pull-down resistors that affect the input current.
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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