ASM5P2308AF-3-16-SR datasheet, PDF

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ASM5P2308AF-3-16-SR: Description3.3V Zero-Delay Buffer; Categorylogic logic; File Size383KB，18 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]; Environmental Compliance

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ASM5P2308AF-3-16-SR Overview

3.3V Zero-Delay Buffer

ASM5P2308AF-3-16-SR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	ALSC [Alliance Semiconductor Corporation]
Parts packaging code	SOIC
package instruction	SOP,
Contacts	16
Reach Compliance Code	unknow
series	2308
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G16
length	9.905 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	16
Actual output times	8
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.4 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm
minfmax	133 MHz

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September 2005

rev 1.4

3.3V Zero-Delay Buffer

General Features

•

Zero input - output propagation delay, adjustable by

capacitive load on FBK input.

•

Multiple configurations - Refer “ASM5P2308A

Configurations “ Table.

•

Input frequency range: 15MHz to 133MHz

Multiple low-skew outputs.

•

Output-output skew less than 200pS.

Device-device skew less than 700pS.

The

ASM5P2308A

allows the input clock to be directly applied to the outputs

for chip and system testing purposes.

Multiple ASM5P2308A devices can accept the same input

clock and distribute it. In this case the skew between the

outputs of the two devices is guaranteed to be less than

700pS.

available

five

different

Two banks of four outputs, tri-stateable by two select

inputs.

configurations(Refer “ASM5P2308A Configurations” Table).

The ASM5P2308A-1 is the base part, where the output

frequencies equal the reference if there is no counter in the

feedback path. The ASM5P2308A-1H is the high-drive

version of the -1 and the rise and fall times on this device

are much faster.

•

Less than 200pS cycle-to-cycle jitter

(-1, -1H,-2, -3, -4, -5H).

•

Available in 16 pin SOIC and TSSOP packages.

3.3V operation.

Advanced 0.35µ CMOS technology.

Industrial temperature available.

The ASM5P2308A-2 allows the user to obtain 2X and 1X

frequencies on each output bank. The exact configuration

Functional Description

ASM5P2308A is a versatile, 3.3V zero-delay buffer

designed to distribute high-speed clocks. It is available in a

16 pin package. The part has an on-chip PLL which locks

to an input clock presented on the REF pin. The PLL

feedback is required to be driven to FBK pin, and can be

obtained from one of the outputs. The input-to-output

propagation delay is guaranteed to be less than 250pS,

and the output-to-output skew is guaranteed to be less than

200pS.

and output frequencies depends on which output drives the

feedback pin. The ASM5P2308A-3 allows the user to

obtain 4X and 2X frequencies on the outputs.

The ASM5P2308A-4 enables the user to obtain 2X clocks

on all outputs.

The ASM5P2308A-5H is a high-drive version with REF/2

on both banks. Thus, the part is extremely versatile, and

can be used in a variety of applications.

The ASM5P2308A has two banks of four outputs each,

which can be controlled by the select inputs as shown in

the Select Input Decoding Table. The select input also

Alliance Semiconductor

2575 Augustine Drive

•

Santa Clara, CA

•

Tel: 408.855.4900

•

Fax: 408.855.4999

•

www.alsc.com

Notice: The information in this document is subject to change without notice.

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