Standard ICs
LCD segment driver
BU9706KS
The BU9706KS is a 40-output LCD segment driver provided with a 40-bit shift register and a 40-bit latch.
As the 40-bit shift register can be divided into two 20-bit sections, it can be used efficiently, based on the number of
segments and the character configuration.
Also, by using a number of BU9706KS drivers, it is possible to configure an LCD segment driver of more than 80
bits.
As the liquid crystal drive voltage can be set externally to any value, it can be used as a driver IC for both static and
dynamic drive in various types of liquid crystal display panels.
•
Featuresshift register and 40-bit latch enable serial
1) 40-bit
input - parallel output.
2) Shift register can be divided into two 20-bit sections.
3) Power supply voltage: 3.5 to 6V.
4) LCD drive voltage: 3 to 6V.
5) Can accommodates duty of 1 / 8 to 1 / 16.
6) Can be used as a driver IC for static drive by setting
the liquid crystal drive voltage externally (V3 = V
DD
,
V2 = V5 = V
SS
, connect DF as LCD common).
•
Block diagram
O
1
41
O
2
40
O
3
39
O
38
O
39
O
40
4
3
2
V
DD
49
V
2
43
V
3
44
V
5
45
DF 51
40 bit Latch
LCD Dr
40
LOAD 47
20
DI
I
53
CP 48
V
SS
42
D
20 bit SHIFT REGISTER
20
D
20-bit SHIFT REGISTER
1
DO
40
CK
CK
54
55
DO
20
DI
21
1
Standard ICs
BU9706KS
SS
•
Absolute maximum ratings (Ta = 25°C, V
Parameter
Power supply voltage
LCD power supply voltage
∗
Input voltage
Power dissipation
Operating temperature
Storage temperature
= 0V)
Limits
– 0.3 ~ + 6.5
0 ~ + 6.5
V
SS
– 0.3 ~ V
DD
+ 0.3
500
– 20 ~ + 70
– 55 ~ + 125
V
3
> V
5
V
SS
.
Symbol
V
DD
V
DD
– V
5
V
IN
Pd
Topr
Tstg
Unit
V
V
V
mW
°C
°C
∗
The LCD power supply voltage must satisfy the condition of V
DD
> V
2
•
Recommended operating conditions (Ta = 25°C, V
Parameter
Power supply voltage
LCD power supply voltage
∗
Input voltage
Symbol
V
DD
V
DD
– V
5
V
IN
SS
= 0V)
Typ.
—
—
—
V
3
> V
5
V
SS
.
Min.
3.5
3.0
0
Max.
6.0
6.0
V
DD
Unit
V
V
V
∗
The LCD power supply voltage must satisfy the condition of V
DD
> V
2
V
SS
O
1
O
10
O
11
O
12
42 41 40 39 38 37 36 35 34 33 32 31 30 29
V
2
V
3
V
5
N.C.
LOAD
CP
V
DD
N.C.
DF
N.C.
DI
1
DO
20
DI
21
N.C.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
2
3
O
39
4 5
O
38
O
37
6
O
36
7 8
O
35
O
34
9 10 11 12 13 14
O
33
O
32
O
31
O
30
O
29
O
28
28
27
26
25
24
23
O
14
O
15
O
16
O
17
O
18
O
19
O
20
O
21
O
22
O
23
O
24
O
25
O
26
O
27
O
13
22
21
20
19
18
17
16
15
•
Pin assignments
O
2
O
3
O
4
O
5
O
6
O
7
O
8
O
9
BU9706KS
2
DO
40
O
40
Standard ICs
BU9706KS
•
Pin descriptions
Pin No.
2 ~ 41
43 ~ 45
49
42
53
Pin name
O
40
~ O
1
V
2
~ V
5
V
DD
V
SS
DI
1
I/O
O
—
—
—
I
Function
Output pin for the liquid crystal driver. V
DD
, V
2
, V
3
or V
5
is output depending on
the latch content and the DF signal. Refer to the truth table for the output level.
Power supply pin for liquid crystal drive
Logic power supply pin and liquid crystal drive power supply pin
Logic power supply pin
Data input pin for the shift register (1 to 20 bits). Data is read to the first bit of
the shift register at the clock signal falling edge.
Data output pin for the shift register (1 to 20 bits). Data is output in
synchronization with the clock signal falling edge. A 40-bit shift register is
accomplished by connecting pins 54 and 55.
Data input pin for the shift register (21 to 40 bits). Data is read to the 21st bit
of the shift register at the clock signal falling edge.
Data output pin for the shift register (21 to 40 bits). Data is output in synchronization
with the clock signal falling edge. It is used to configure an LCD driver with more
than 40 bits by connecting it to the DI pin of the BU9706KS at the next stage.
Clock signal input pin for the shift register. The contents of the shift register
are shifted by 1 bit only at the clock signal falling edge.
Latch signal input pin for the 40-bit latch. The contents of the shift register are
transferred to O
1
to O
40
at LOAD = "H" and the data is latched at LOAD = "L". While
LOAD = "L", the latched data is held even if the contents of the shift register change.
Input pin for the signal which produces AC for LCD drive.
54
DO
20
O
55
DI
21
I
1
DO
40
O
48
CP
I
47
51
LOAD
DF
I
I
•
LCD drive output pin truth table
Latch data
H
H
L
L
DF
H
L
H
L
O
n
terminal voltage
V
5
V
DD
V
3
V
2
•
Timing chart
CP
DI
1
40
1
2
3
39
40
1
2
O
1
Load
O
40
O
39
O
38
O
2
O
1
Load
O
40
O
39
LOAD
DF
• Shifted at CP input falling.
• When the LOAD input state becomes "H", the contents of the shift register are transferred to the segment
outputs O
1
to O
40
, and when it is "L", the data is latched.
Fig.1
3
Standard ICs
BU9706KS
DD
•
Electrical characteristics (unless otherwise noted, Ta = 25°C, V
DC characteristics
Parameter
Input high level voltage
∗
1
Input low level voltage
∗
1
Input high level current
∗
1
Input low level current
∗
1
Output high level voltage
∗
2
Output low level voltage
∗
2
ON resistance
∗
3
∗
4
Current dissipation
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
R
ON
I
DD
Min.
4.0
—
—
—
4.2
—
—
—
Typ.
—
—
—
—
—
—
—
—
Max.
—
1.0
1
–1
—
0.4
5
0.5
= 5 V)
Unit
V
V
µA
µA
V
V
kΩ
mA
V
IH
= V
DD
V
IL
= 0V
I
O
= – 40µA
I
O
= 0.4mA
| V
IN
– V
O
|
∗
5
= 0.25V
CP = DC No load
Conditions
—
—
∗
1 Applied to DF, LOAD, CP, DI
1
and DI
21
pins
∗
2 Applied to DO
20
and DO
40
pins
∗
3 Applied to O
1
to O
40
pins
∗
4 V
DD
= 5V, V
2
= 2 / 3 V
DD
, V
3
= 1 / 3 V
DD
, V
5
= 0V
∗
5 V
IN
= V
DD
, V
2
, V
3
, V
5
, V
o
= O pin voltage
n
AC characteristics
Parameter
Propagation delay time 1
Propagation delay time 2
∗
Propagation delay time 3
∗
DI
→
CP setup time
CP
→
DI hold time
CP pulse width
Load pulse width
CP
→
load time
LOAD
→
CP time
Maximum clock frequency
Not designed for radiation resistance.
Symbol
t
pLH
, t
pHL
t
p (L)
t
p (D)
t
sLH
, t
sHL
t
hLH
, t
hHL
t
w (CP)
t
w (L)
t
CL
t
LC
f
CP
Min.
—
—
—
50
50
125
125
250
0
3.3
Typ.
—
—
—
—
—
—
—
—
—
—
Max.
250
250
250
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
DUTY = 50%
Conditions
CP
→
DO
n
delay time
Load
→
O
n
delay time
DF
→
O
n
delay time
—
—
—
—
—
—
∗
V
DD
= 5V, V
2
= 2 / 3V
DD,
V
3
= 1 / 3V
DD,
V
5
= 0V
4
Standard ICs
BU9706KS
tw
(CP)
CP
0.8V
DD
0.8V
DD
tw
(CP)
0.8V
DD
0.2V
DD
0.2V
DD
t
hLH
t
hHL
0.8V
DD
0.2V
DD
t
pLH
t
pHL
t
sLH
t
sHL
DI
1,
DI
21
DO
20,
DO
40
0.8V
DD
0.2V
DD
t
CL
t
LC
0.2V
DD
LOAD
0.8V
DD
0.8V
DD
t
W (L)
O
1
~ O
40
t
p (L)
∗
∗
DF
0.8V
DD
t
p (D)
0.2V
DD
t
p (D)
O
1
~ O
40
∗
∗
∗
∗
∗
t
p (L)
and t
p (D)
are times required before the O
1
to O
40
output amplitude becomes 80% and 20% respectively.
Fig.2 AC characteristics waveform
•
Application example
COM
1
LCD panel (16 commons, 120 segments)
COM
16
SEG
1
SEG
40
D
Controller
O
1
DI
1
DO
20
DI
21
O
40
DO
40
BU9706KS
O
1
DI
1
DO
20
DI
21
O
40
DO
40
BU9706KS
R
LOAD
V
DD
LOAD
CP
CP
DF
DF
V
2
V
3
V
5
V
2
V
1
V
2
V
3
V
4
V
5
M
CL
1
CL
2
V
3
V
5
R
R
R
R
Fig.3
5
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