R
3
9
Platform Flash In-System Programmable
Configuration PROMS
Preliminary Product Specification
DS123 (v2.4) July 20, 2004
0
Features
•
•
•
•
•
•
•
•
•
•
In-System Programmable PROMs for Configuration of
Xilinx FPGAs
Low-Power Advanced CMOS FLASH Process
Endurance of 20,000 Program/Erase Cycles
Operation over Full Industrial Temperature Range
(–40°C to +85°C)
IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)
Support for Programming, Prototyping, and Testing
JTAG Command Initiation of Standard FPGA
Configuration
Cascadable for Storing Longer or Multiple Bitstreams
Dedicated Boundary-Scan (JTAG) I/O Power Supply
(V
CCJ
)
I/O Pins Compatible with Voltage Levels Ranging From
1.5V to 3.3V
Design Support Using the Xilinx Alliance ISE and
Foundation ISE Series Software Packages
•
•
XCF01S/XCF02S/XCF04S
- 3.3V supply voltage
- Serial FPGA configuration interface (up to 33 MHz)
- Available in small-footprint VO20 and VOG20
packages.
XCF08P/XCF16P/XCF32P
- 1.8V supply voltage
- Serial or parallel FPGA configuration interface
(up to 33 MHz)
- Available in small-footprint VO48, VOG48, FS48,
and FSG48 packages
- Design revision technology enables storing and
accessing multiple design revisions for
configuration
- Built-in data decompressor compatible with Xilinx
advanced compression technology
Table 1:
Platform Flash PROM Features
Density
V
CCINT
V
CCO
/ V
CCJ
Range
Packages
JTAG ISP
Serial
Parallel
Programming Configuration Configuration
Design
Revisioning
Compression
XCF01S
XCF02S
XCF04S
XCF08P
XCF16P
XCF32P
1 Mbit
2 Mbit
4 Mbit
8 Mbit
16 Mbit
32 Mbit
3.3V
3.3V
3.3V
1.8V
1.8V
1.8V
1.8V - 3.3V
1.8V - 3.3V
1.8V - 3.3V
1.5V - 3.3V
1.5V - 3.3V
1.5V - 3.3V
VO20/VOG28
VO20/VOG28
VO20/VOG28
VO48/VOG48
FS48/FSG48
VO48/VOG48
FS48/FSG48
VO48/VOG48
FS48/FSG48
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Description
Xilinx introduces the Platform Flash series of in-system pro-
grammable configuration PROMs. Available in 1 to 32
Megabit (Mbit) densities, these PROMs provide an
easy-to-use, cost-effective, and reprogrammable method
for storing large Xilinx FPGA configuration bitstreams. The
Platform Flash PROM series includes both the 3.3V
XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS
version includes 4-Mbit, 2-Mbit, and 1-Mbit PROMs that
support Master Serial and Slave Serial FPGA configuration
modes (Figure
1).
The XCFxxP version includes 32-Mbit,
16-Mbit, and 8-Mbit PROMs that support Master Serial,
Slave Serial, Master SelectMAP, and Slave SelectMAP
FPGA configuration modes (Figure
2).
A summary of the
Platform Flash PROM family members and supported fea-
tures is shown in
Table 1.
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS123 (v2.4) July 20, 2004
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1
R
Platform Flash In-System Programmable Configuration PROMS
CLK
CE
OE/RESET
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Data
Memory
Address
Data
Serial
Interface
CEO
DATA (D0)
Serial Mode
CF
ds123_01_30603
Figure 1:
XCFxxS Platform Flash PROM Block Diagram
FI
CLK
CE
EN_EXT_SEL
OE/RESET
BUSY
CLKOUT
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
OSC
Data
Address
Memory
Data
Serial
or
Parallel
Interface
CEO
DATA (D0)
(Serial/Parallel Mode)
D[1:7]
(Parallel Mode)
Decompressor
CF
REV_SEL [1:0]
ds123_19_050604
Figure 2:
XCFxxP Platform Flash PROM Block Diagram
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. With CF High, a
short access time after CE and OE are enabled, data is
available on the PROM DATA (D0) pin that is connected to
the FPGA DIN pin. New data is available a short access
time after each rising clock edge. The FPGA generates the
appropriate number of clock pulses to complete the config-
uration.
When the FPGA is in Slave Serial mode, the PROM and the
FPGA are both clocked by an external clock source, or
optionally, for the XCFxxP PROM only, the PROM can be
used to drive the FPGA’s configuration clock.
The XCFxxP version of the Platform Flash PROM also sup-
ports Master SelectMAP and Slave SelectMAP (or Slave
Parallel) FPGA configuration modes. When the FPGA is in
Master SelectMAP mode, the FPGA generates a configura-
tion clock that drives the PROM. When the FPGA is in Slave
SelectMAP Mode, either an external oscillator generates
the configuration clock that drives the PROM and the
FPGA, or optionally, the XCFxxP PROM can be used to
drive the FPGA’s configuration clock. With BUSY Low and
CF High, after CE and OE are enabled, data is available on
the PROMs DATA (D0-D7) pins. New data is available a
short access time after each rising clock edge. The data is
clocked into the FPGA on the following rising edge of the
CCLK. A free-running oscillator can be used in the Slave
Parallel /Slave SelecMAP mode.
The XCFxxP version of the Platform Flash PROM provides
additional advanced features. A built-in data decompressor
supports utilizing compressed PROM files, and design revi-
sioning allows multiple design revisions to be stored on a
single PROM or stored across several PROMs. For design
revisioning, external pins or internal control bits are used to
select the active design revision.
Multiple Platform Flash PROM devices can be cascaded to
support the larger configuration files required when target-
ing larger FPGA devices or targeting multiple FPGAs daisy
chained together. When utilizing the advanced features for
the XCFxxP Platform Flash PROM, such as design revi-
sioning, programming files which span cascaded PROM
devices can only be created for cascaded chains containing
only XCFxxP PROMs. If the advanced XCFxxP features are
DS123 (v2.4) July 20, 2004
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
2
R
Platform Flash In-System Programmable Configuration PROMS
Table 2:
Xilinx FPGAs and Compatible Platform Flash
PROMs
(Continued)
FPGA
Virtex
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
1,305,440
3,006,560
4,485,472
8,214,624
11,589,984
15,868,256
19,021,408
26,099,040
34,292,832
338,976
598,816
1,593,632
2,560,544
4,082,592
5,170,208
6,812,960
10,494,368
15,659,936
21,849,504
26,194,208
630,048
863,840
1,442,016
1,875,648
2,693,440
3,430,400
3,961,632
6,519,648
6,587,520
8,308,992
10,159,648
12,922,336
16,283,712
XCF02S
XCF04S
XCF08P
XCF08P
XCF16P
XCF16P
XCF32P
XCF32P
XCF32P
(2)
XCF01S
XCF01S
XCF02S
XCF04S
XCF04S
XCF08P
XCF08P
XCF16P
XCF16P
XCF32P
XCF32P
XCF01S
XCF01S
XCF02S
XCF02S
XCF04S
XCF04S
XCF04S
XCF08P
XCF08P
XCF08P
XCF16P
XCF16P
XCF16P
XCV800
XCV1000
559,200
781,216
1,040,096
1,335,840
1,751,808
2,546,048
3,607,968
4,715,616
6,127,744
439,264
1,047,616
1,699,136
3,223,488
5,214,784
7,673,024
11,316,864
13,271,936
630,048
863,840
1,134,496
1,442,016
1,875,648
2,693,440
3,961,632
197,696
336,768
559,200
781,216
1,040,096
1,335,840
XCF01S
XCF01S
XCF01S
XCF02S
XCF02S
XCF04S
XCF04S
XCF08P
XCF08P
XCF01S
XCF01S
XCF02S
XCF04S
XCF08P
XCF08P
XCF16P
XCF16P
XCF01S
XCF01S
XCF02S
XCF02S
XCF02S
XCF04S
XCF04S
XCF01S
XCF01S
XCF01S
XCF01S
XCF01S
XCF02S
not enabled, then the cascaded chain can include both
XCFxxP and XCFxxS PROMs.
The Platform Flash PROMs are compatible with all of the
existing FPGA device families. A reference list of Xilinx
FPGAs and the respective compatible Platform Flash
PROMs is given in
Table 2.
A list of Platform Flash PROMs
and their capacities is given in
Table 3.
Table 2:
Xilinx FPGAs and Compatible Platform Flash
PROMs
FPGA
Virtex-II Pro
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP100
Configuration
Bitstream
Platform Flash
PROM
(1)
Configuration
Bitstream
Platform Flash
PROM
(1)
Spartan-3
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Virtex-II
XC2V40
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
Spartan-IIE
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
Spartan-II
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Virtex-E
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV405E
XCV600E
XCV812E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
Notes:
1. If design revisioning or other advanced feature support is required,
the XCFxxP can be used as an alternative to the XCF01S, XCF02S,
or XCF04S.
2. Assumes compression used.
Table 3:
Platform Flash PROM Capacity
Platform
Flash PROM
Configuration
Bits
Platform Flash
PROM
Configuration
Bits
XCF01S
XCF02S
XCF04S
1,048,576
2,097,152
4,194,304
XCF08P
XCF16P
XCF32P
8,388,608
16,777,216
33,554,432
DS123 (v2.4) July 20, 2004
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
3
R
Platform Flash In-System Programmable Configuration PROMS
Programming
In-System Programming
In-System Programmable PROMs can be programmed indi-
vidually, or two or more can be daisy-chained together and
programmed in-system via the standard 4-pin JTAG proto-
col as shown in
Figure 3.
In-system programming offers
quick and efficient design iterations and eliminates unnec-
essary package handling or socketing of devices. The pro-
gramming data sequence is delivered to the device using
either Xilinx iMPACT software and a Xilinx download cable,
a third-party JTAG development system, a JTAG-compatible
board tester, or a simple microprocessor interface that emu-
lates the JTAG instruction sequence. The iMPACT software
also outputs serial vector format (SVF) files for use with any
tools that accept SVF format, including automatic test
equipment. During in-system programming, the CEO output
is driven High. All other outputs are held in a high-imped-
ance state or held at clamp levels during in-system pro-
gramming. In-system programming is fully supported
across the recommended operating voltage and tempera-
ture ranges.
programmer. This provides the added flexibility of using
pre-programmed devices with an in-system programmable
option for future enhancements and design changes.
Reliability and Endurance
Xilinx in-system programmable products provide a guaran-
teed endurance level of 20,000 in-system program/erase
cycles and a minimum data retention of 20 years. Each
device meets all functional, performance, and data retention
specifications within this endurance limit.
Design Security
The Xilinx in-system programmable Platform Flash PROM
devices incorporate advanced data security features to fully
protect the FPGA programming data against unauthorized
reading via JTAG. The XCFxxP PROMs can also be pro-
grammed to prevent inadvertent writing via JTAG.
Table 4
and
Table 5
show the security settings available for the
XCFxxS PROM and XCFxxP PROM, respectively.
Read Protection
The read protect security bit can be set by the user to pre-
vent the internal programming pattern from being read or
copied via JTAG. Read protection does not prevent write
operations. For the XCFxxS PROM, the read protect secu-
rity bit is set for the entire device, and resetting the read pro-
tect security bit requires erasing the entire device. For the
XCFxxP PROM the read protect security bit can be set for
individual design revisions, and resetting the read protect bit
requires erasing the particular design revision.
GND
V
CC
Write Protection
(a)
(b)
DS026_02_082703
Figure 3:
JTAG In-System Programming Operation
(a) Solder Device to PCB
(b) Program Using Download Cable
OE/RESET
The 1/2/4 Mbit XCFxxS Platform Flash PROMs in-system
programming algorithm requires issuance of a reset that
causes OE/RESET to pulse Low.
The XCFxxP PROM device also allows the user to write
protect (or lock) a particular design revision to prevent inad-
vertent erase or program operations. Once set, the write
protect security bit for an individual design revision must be
reset (using the UNLOCK command followed by
ISC_ERASE command) before an erase or program opera-
tion can be performed.
Table 4:
XCFxxS Device Data Security Options
Read Protect
Reset (default)
Set
√
Read/Verify
Inhibited
Program
Inhibited
Erase
Inhibited
External Programming
Xilinx reprogrammable PROMs can also be programmed by
the Xilinx MultiPRO Desktop Tool or a third-party device
DS123 (v2.4) July 20, 2004
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
4
R
Platform Flash In-System Programmable Configuration PROMS
Table 5:
XCFxxP Design Revision Data Security Options
Read Protect
Reset (default)
Reset (default)
Set
Set
Write Protect
Reset (default)
Set
Reset (default)
Set
√
√
√
√
√
√
Read/Verify
Inhibited
Program
Inhibited
Erase Inhibited
IEEE 1149.1 Boundary-Scan (JTAG)
The Platform Flash PROM family is IEEE Standard 1532
in-system programming compatible, and is fully compliant
with the IEEE Std. 1149.1 Boundary-Scan, also known as
JTAG, which is a subset of IEEE Std. 1532 Boundary-Scan.
A Test Access Port (TAP) and registers are provided to sup-
port all required boundary scan instructions, as well as
many of the optional instructions specified by IEEE Std.
1149.1. In addition, the JTAG interface is used to implement
in-system programming (ISP) to facilitate configuration, era-
sure, and verification operations on the Platform Flash
PROM device.
Table 6
lists the required and optional
boundary-scan instructions supported in the Platform Flash
PROMs. Refer to the IEEE Std. 1149.1 specification for a
complete description of boundary-scan architecture and the
required and optional instructions.
to a logic "0". The ISC Status field, IR[4], contains logic "1"
if the device is currently in In-System Configuration (ISC)
mode; otherwise, it contains logic "0". The Security field,
IR[3], contains logic "1" if the device has been programmed
with the security option turned on; otherwise, it contains
logic "0". IR[2] is unused, and is set to '0'. The remaining bits
IR[1:0] are set to '01' as defined by IEEE Std. 1149.1.
XCFxxP Instruction Register (16 bits wide)
The Instruction Register (IR) for the XCFxxP PROM is six-
teen bits wide and is connected between TDI and TDO dur-
ing an instruction scan sequence. The detailed composition
of the instruction capture pattern is illustrated in
Figure 5.
The instruction capture pattern shifted out of the XCFxxP
device includes IR[15:0]. IR[15:9] are reserved bits and are
set to a logic "0". The ISC Error field, IR[8:7], contains a "10"
when an ISC operation is a success, otherwise a "01" when
an In-System Configuration (ISC) operation fails The
Erase/Program (ER/PROG) Error field, IR[6:5], contains a
"10" when an erase or program operation is a success, oth-
erwise a "01" when an erase or program operation fails. The
Erase/Program (ER/PROG) Status field, IR[4], contains a
logic "1" when the device is busy performing an erase or
programming operation, otherwise, it contains a logic "0".
The ISC Status field, IR[3], contains logic "1" if the device is
currently in In-System Configuration (ISC) mode; otherwise,
it contains logic "0". The DONE field, IR[2], contains logic
"1" if the sampled design revision has been successfully
programmed; otherwise, a logic "0" indicates incomplete
programming. The remaining bits IR[1:0] are set to '01' as
defined by IEEE Std. 1149.1.
Instruction Register
The Instruction Register (IR) for the Platform Flash PROM
is connected between TDI and TDO during an instruction
scan sequence. In preparation for an instruction scan
sequence, the instruction register is parallel loaded with a
fixed instruction capture pattern. This pattern is shifted out
onto TDO (LSB first), while an instruction is shifted into the
instruction register from TDI.
XCFxxS Instruction Register (8 bits wide)
The Instruction Register (IR) for the XCFxxS PROM is eight
bits wide and is connected between TDI and TDO during an
instruction scan sequence. The detailed composition of the
instruction capture pattern is illustrated in
Figure 4.
The instruction capture pattern shifted out of the XCFxxS
device includes IR[7:0]. IR[7:5] are reserved bits and are set
DS123 (v2.4) July 20, 2004
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
5
Microcontroller MCU
京公网安备 11010802033920号
EEWORLD
