0
R
Virtex™ 2.5 V
Field Programmable Gate Arrays
0
3
DS003-2 (v2.5) April 2, 2001
Product Specification
The output buffer and all of the IOB control signals have
independent polarity controls.
Architectural Description
Virtex Array
The Virtex user-programmable gate array, shown in
Figure 1,
comprises two major configurable elements: con-
figurable logic blocks (CLBs) and input/output blocks
(IOBs).
•
•
CLBs provide the functional elements for constructing
logic
IOBs provide the interface between the package pins
and the CLBs
DLL
IOBs
VersaRing
DLL
VersaRing
VersaRing
BRAMs
BRAMs
IOBs
IOBs
CLBs interconnect through a general routing matrix (GRM).
The GRM comprises an array of routing switches located at
the intersections of horizontal and vertical routing channels.
Each CLB nests into a VersaBlock™ that also provides local
routing resources to connect the CLB to the GRM.
The VersaRing™ I/O interface provides additional routing
resources around the periphery of the device. This routing
improves I/O routability and facilitates pin locking.
The Virtex architecture also includes the following circuits
that connect to the GRM.
•
•
•
Dedicated block memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
3-State buffers (BUFTs) associated with each CLB that
drive dedicated segmentable horizontal routing
resources
CLBs
VersaRing
DLL
IOBs
DLL
vao_b.eps
Figure 1:
Virtex Architecture Overview
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. Two
forms of over-voltage protection are provided, one that per-
mits 5 V compliance, and one that does not. For 5 V compli-
ance, a Zener-like structure connected to ground turns on
when the output rises to approximately 6.5 V. When PCI
3.3 V compliance is required, a conventional clamp diode is
connected to the output supply voltage, V
CCO
.
Optional pull-up and pull-down resistors and an optional
weak-keeper circuit are attached to each pad. Prior to con-
figuration, all pins not involved in configuration are forced
into their high-impedance state. The pull-down resistors and
the weak-keeper circuits are inactive, but inputs can option-
ally be pulled up.
The activation of pull-up resistors prior to configuration is
controlled on a global basis by the configuration mode pins.
If the pull-up resistors are not activated, all the pins will float.
Consequently, external pull-up or pull-down resistors must
be provided on pins required to be at a well-defined logic
level prior to configuration.
All Virtex IOBs support IEEE 1149.1-compatible boundary
scan testing.
Values stored in static memory cells control the configurable
logic elements and interconnect resources. These values
load into the memory cells on power-up, and can reload if
necessary to change the function of the device.
Input/Output Block
The Virtex IOB,
Figure 2,
features SelectIO™ inputs and
outputs that support a wide variety of I/O signalling stan-
dards, see
Table 1.
The three IOB storage elements function either as edge-trig-
gered D-type flip-flops or as level sensitive latches. Each
IOB has a clock signal (CLK) shared by the three flip-flops
and independent clock enable signals for each flip-flop.
In addition to the CLK and CE control signals, the three
flip-flops share a Set/Reset (SR). For each flip-flop, this sig-
nal can be independently configured as a synchronous Set,
a synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS003-2 (v2.5) April 2, 2001
Product Specification
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1
Virtex™ 2.5 V Field Programmable Gate Arrays
R
T
TCE
D Q
CE
Weak
Keeper
SR
O
OCE
D Q
CE
PAD
OBUFT
SR
I
IQ
Q
Programmable
Delay
IBUF
Vref
SR
SR
CLK
ICE
ds022_02_091300
D
CE
Figure 2:
Virtex Input/Output Block (IOB)
Table 1:
Supported Select I/O Standards
I/O Standard
LVTTL 2 – 24 mA
LVCMOS2
PCI, 5 V
PCI, 3.3 V
GTL
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL3 Class I &II
SSTL2 Class I & II
CTT
AGP
Input Reference
Voltage (V
REF
)
N/A
N/A
N/A
N/A
0.8
1.0
0.75
0.9
0.9
1.5
1.25
1.5
1.32
Output Source
Voltage (V
CCO
)
3.3
2.5
3.3
3.3
N/A
N/A
1.5
1.5
1.5
3.3
2.5
3.3
3.3
Board Termination
Voltage (V
TT
)
N/A
N/A
N/A
N/A
1.2
1.5
0.75
1.5
1.5
1.5
1.25
1.5
N/A
5 V Tolerant
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
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DS003-2 (v2.5) April 2, 2001
Product Specification
R
Virtex™ 2.5 V Field Programmable Gate Arrays
Eight I/O banks result from separating each edge of the
FPGA into two banks, as shown in
Figure 3.
Each bank has
multiple V
CCO
pins, all of which must be connected to the
same voltage. This voltage is determined by the output
standards in use.
Input Path
A buffer In the Virtex IOB input path routes the input signal
either directly to internal logic or through an optional input
flip-flop.
An optional delay element at the D-input of this flip-flop elim-
inates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signalling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, V
REF
. The need to supply V
REF
imposes
constraints on which standards can used in close proximity
to each other. See
I/O Banking,
page 3.
There are optional pull-up and pull-down resistors at each
input for use after configuration. Their value is in the range
50 k
W
– 100 k
W
.
Bank 0
Bank 7
Bank 1
Bank 2
GCLK3 GCLK2
Virtex
Device
Bank 6
GCLK1 GCLK0
Bank 5
Bank 4
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides syn-
chronous enable and disable.
Each output driver can be individually programmed for a
wide range of low-voltage signalling standards. Each output
buffer can source up to 24 mA and sink up to 48mA. Drive
strength and slew rate controls minimize bus transients.
In most signalling standards, the output High voltage
depends on an externally supplied V
CCO
voltage. The need
to supply V
CCO
imposes constraints on which standards
can be used in close proximity to each other. See
I/O Bank-
ing,
page 3.
An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way eliminates bus chatter.
Because the weak-keeper circuit uses the IOB input buffer
to monitor the input level, an appropriate V
REF
voltage must
be provided if the signalling standard requires one. The pro-
vision of this voltage must comply with the I/O banking
rules.
Figure 3:
X8778_b
Virtex I/O Banks
Within a bank, output standards can be mixed only if they
use the same V
CCO
. Compatible standards are shown in
Table 2.
GTL and GTL+ appear under all voltages because
their open-drain outputs do not depend on V
CCO
.
Table 2:
Compatible Output Standards
V
CCO
3.3 V
2.5 V
1.5 V
Compatible Standards
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,
GTL+
SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+
HSTL I, HSTL III, HSTL IV, GTL, GTL+
Some input standards require a user-supplied threshold
voltage, V
REF
. In this case, certain user-I/O pins are auto-
matically configured as inputs for the V
REF
voltage. Approx-
imately one in six of the I/O pins in the bank assume this
role.
The V
REF
pins within a bank are interconnected internally
and consequently only one V
REF
voltage can be used within
each bank. All V
REF
pins in the bank, however, must be con-
nected to the external voltage source for correct operation.
Within a bank, inputs that require V
REF
can be mixed with
those that do not. However, only one V
REF
voltage can be
used within a bank. Input buffers that use V
REF
are not 5 V
tolerant. LVTTL, LVCMOS2, and PCI 33 MHz 5 V, are 5 V
tolerant.
The V
CCO
and V
REF
pins for each bank appear in the device
Pinout tables and diagrams. The diagrams also show the
bank affiliation of each I/O.
Within a given package, the number of V
REF
and V
CCO
pins
can vary depending on the size of device. In larger devices,
I/O Banking
Some of the I/O standards described above require V
CCO
and/or V
REF
voltages. These voltages externally and con-
nected to device pins that serve groups of IOBs, called
banks. Consequently, restrictions exist about which I/O
standards can be combined within a given bank.
DS003-2 (v2.5) April 2, 2001
Product Specification
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Bank 3
Module 2 of 4
3
Virtex™ 2.5 V Field Programmable Gate Arrays
more I/O pins convert to V
REF
pins. Since these are always
a superset of the V
REF
pins used for smaller devices, it is
possible to design a PCB that permits migration to a larger
device if necessary. All the V
REF
pins for the largest device
anticipated must be connected to the V
REF
voltage, and not
used for I/O.
In smaller devices, some V
CCO
pins used in larger devices
do not connect within the package. These unconnected pins
can be left unconnected externally, or can be connected to
the V
CCO
voltage to permit migration to a larger device if
necessary.
In TQ144 and PQ/HQ240 packages, all V
CCO
pins are
bonded together internally, and consequently the same
V
CCO
voltage must be connected to all of them. In the
CS144 package, bank pairs that share a side are intercon-
nected internally, permitting four choices for V
CCO
. In both
cases, the V
REF
pins remain internally connected as eight
banks, and can be used as described previously.
R
of five or six inputs. Consequently, when estimating the
number of system gates provided by a given device, each
CLB counts as 4.5 LCs.
Look-Up Tables
Virtex function generators are implemented as 4-input
look-up tables (LUTs). In addition to operating as a function
generator, each LUT can provide a 16 x 1-bit synchronous
RAM. Furthermore, the two LUTs within a slice can be com-
bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,
or a 16x1-bit dual-port synchronous RAM.
The Virtex LUT can also provide a 16-bit shift register that is
ideal for capturing high-speed or burst-mode data. This
mode can also be used to store data in applications such as
Digital Signal Processing.
Storage Elements
The storage elements in the Virtex slice can be configured
either as edge-triggered D-type flip-flops or as level-sensi-
tive latches. The D inputs can be driven either by the func-
tion generators within the slice or directly from slice inputs,
bypassing the function generators.
In addition to Clock and Clock Enable signals, each Slice
has synchronous set and reset signals (SR and BY). SR
forces a storage element into the initialization state speci-
fied for it in the configuration. BY forces it into the opposite
state. Alternatively, these signals can be configured to oper-
ate asynchronously. All of the control signals are indepen-
dently invertible, and are shared by the two flip-flops within
the slice.
Configurable Logic Block
The basic building block of the Virtex CLB is the logic cell
(LC). An LC includes a 4-input function generator, carry
logic, and a storage element. The output from the function
generator in each LC drives both the CLB output and the D
input of the flip-flop. Each Virtex CLB contains four LCs,
organized in two similar slices, as shown in
Figure 4.
Figure 5
shows a more detailed view of a single slice.
In addition to the four basic LCs, the Virtex CLB contains
logic that combines function generators to provide functions
COUT
COUT
G4
G3
G2
G1
RC
LUT
Carry &
Control
SP
D Q
EC
YB
Y
YQ
G4
G3
G2
G1
RC
LUT
Carry &
Control
SP
D Q
EC
YB
Y
YQ
BY
BY
XB
X
XB
F4
F3
LUT
F2
F1
RC
Slice 0
Carry &
Control
SP
D Q
EC
X
XQ
F4
F3
F2
F1
LUT
Carry &
Control
SP
D Q
EC
XQ
BX
RC
Slice 1
BX
slice_b.eps
CIN
CIN
Figure 4:
2-Slice Virtex CLB
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Product Specification
R
Virtex™ 2.5 V Field Programmable Gate Arrays
COUT
YB
CY
G4
G3
G2
G1
I3
I2
I1
I0
O
INIT
D Q
EC
Y
LUT
WE
DI
YQ
0
1
BY
REV
XB
F5IN
F6
CY
F5
F5
X
CK
WE
A4
BX
F4
F3
F2
F1
I3
I2
I1
I0
WSO
WSH
BY DG
BX
DI
INIT
D Q
EC
XQ
WE
DI
O
REV
LUT
0
1
SR
CLK
CE
CIN
viewslc4.eps
Figure 5:
Detailed View of VIrtex Slice
Additional Logic
The F5 multiplexer in each slice combines the function gen-
erator outputs. This combination provides either a function
generator that can implement any 5-input function, a 4:1
multiplexer, or selected functions of up to nine inputs.
Similarly, the F6 multiplexer combines the outputs of all four
function generators in the CLB by selecting one of the
F5-multiplexer outputs. This permits the implementation of
any 6-input function, an 8:1 multiplexer, or selected func-
tions of up to 19 inputs.
Each CLB has four direct feedthrough paths, one per LC.
These paths provide extra data input lines or additional local
routing that does not consume logic resources.
Block SelectRAM
Virtex FPGAs incorporate several large Block SelectRAM
memories. These complement the distributed LUT Selec-
tRAMs that provide shallow RAM structures implemented in
CLBs.
Block SelectRAM memory blocks are organized in columns.
All Virtex devices contain two such columns, one along
each vertical edge. These columns extend the full height of
the chip. Each memory block is four CLBs high, and conse-
quently, a Virtex device 64 CLBs high contains 16 memory
blocks per column, and a total of 32 blocks.
Table 3
shows the amount of Block SelectRAM memory that
is available in each Virtex device.
Table 3:
Virtex Block SelectRAM Amounts
Device
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
# of Blocks
8
10
12
14
16
20
24
28
32
Total Block SelectRAM Bits
32,768
40,960
49,152
57,344
65,536
81,920
98,304
114,688
131,072
Arithmetic Logic
Dedicated carry logic provides fast arithmetic carry capabil-
ity for high-speed arithmetic functions. The Virtex CLB sup-
ports two separate carry chains, one per Slice. The height
of the carry chains is two bits per CLB.
The arithmetic logic includes an XOR gate that allows a
1-bit full adder to be implemented within an LC. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementation.
The dedicated carry path can also be used to cascade func-
tion generators for implementing wide logic functions.
BUFTs
Each Virtex CLB contains two 3-state drivers (BUFTs) that
can drive on-chip busses. See
Dedicated Routing,
page 7.
Each Virtex BUFT has an independent 3-state control pin
and an independent input pin.
DS003-2 (v2.5) April 2, 2001
Product Specification
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