S25FL512S
512 Mbit (64 Mbyte), 3.0 V SPI Flash Memory
Features
CMOS 3.0 Volt Core with Versatile I/O
Serial Peripheral Interface with Multi-I/O
Density
– 512 Mbits (64 Mbytes)
Serial Peripheral Interface (SPI)
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing: 32-bit address
– Serial Command set and footprint compatible with
S25FL-A,
S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad
DDR
– AutoBoot - power up or reset and execute a Normal or
Quad read command automatically at a preselected
address
– Common Flash Interface (CFI) data for configuration
information.
Programming (1.5 MB/s)
– 512-byte Page Programming buffer
– Quad-Input Page Programming (QPP) for slow clock
systems
– Automatic ECC -internal hardware Error Correction Code
generation with single bit error correction
Erase (0.5 to 0.65 MB/s)
– Uniform 256-kbyte sectors
Cycling Endurance
– 100,000 Program-Erase Cycles, minimum
Data Retention
– 20 Year Data Retention, minimum
Security features
– One Time Program (OTP) array of 1024 bytes
– Block Protection:
– Status Register bits to control protection against
program or erase of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or
password
Cypress
®
65 nm MirrorBit
®
Technology with Eclipse
™
Architecture
Core Supply Voltage: 2.7 V to 3.6 V
I/O Supply Voltage: 1.65 V to 3.6 V
– SO16 and FBGA packages
Temperature Range:
– Industrial (–40 °C to +85 °C)
– Industrial Plus (–40 °C to +105 °C)
– Automotive, AEC-Q100 Grade 3 (–40 °C to +85 °C)
– Automotive, AEC-Q100 Grade 2 (–40 °C to +105 °C)
– Automotive, AEC-Q100 Grade 1 (–40 °C to +125 °C)
Packages (all Pb-free)
– 16-lead SOIC (300 mil)
– BGA-24 6 × 8 mm
– 5 × 5 ball (FAB024) and 4 × 6 ball (FAC024) footprint
options
– Known Good Die and Known Tested Die
Logic Block Diagram
CS#
SCK
SI/IO0
SO/IO1
I/O
WP#/IO2
HOLD#/IO3
RESET#
Data Path
Control
Logic
X Decoders
SRAM
MirrorBit Array
Y Decoders
Data Latch
Cypress Semiconductor Corporation
Document Number: 001-98284 Rev. *N
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 15, 2017
S25FL512S
Performance Summary
Maximum Read Rates with the Same Core and I/O Voltage (V
IO
= V
CC
= 2.7 V to 3.6 V)
Command
Read
Fast Read
Dual Read
Quad Read
Clock Rate (MHz)
50
133
104
104
Mbps
6.25
16.6
26
52
Maximum Read Rates with Lower I/O Voltage (V
IO
= 1.65 V to 2.7 V, V
CC
= 2.7 V to 3.6 V)
Command
Read
Fast Read
Dual Read
Quad Read
Clock Rate (MHz)
50
66
66
66
Mbps
6.25
8.25
16.5
33
Maximum Read Rates DDR (V
IO
= V
CC
= 3 V to 3.6 V)
Command
Fast Read DDR
Dual Read DDR
Quad Read DDR
Clock Rate (MHz)
80
80
80
Mbps
20
40
80
Typical Program and Erase Rates
Operation
Page Programming (512-byte page buffer - Uniform Sector Option)
256-kbyte Logical Sector Erase (Uniform Sector Option)
kbytes/s
1500
500
Current Consumption
Operation
Serial Read 50 MHz
Serial Read 133 MHz
Quad Read 104 MHz
Program
Erase
Standby
Clock Rate (MHz)
16 (max)
33 (max)
61 (max)
100 (max)
100 (max)
0.07 (typ)
Document Number: 001-98284 Rev. *N
Page 2 of 133
S25FL512S
Contents
1.
1.1
1.2
1.3
1.4
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
3.
3.1
3.2
3.3
3.4
3.5
4.
4.1
4.2
4.3
4.4
4.5
5.
5.1
5.2
5.3
5.4
5.5
6.
6.1
6.2
6.3
Overview
.......................................................................
General Description .......................................................
Migration Notes..............................................................
Glossary.........................................................................
Other Resources............................................................
4
4
4
6
7
Software Interface
7.
7.1
7.2
7.3
7.4
7.5
7.6
8.
8.1
8.2
8.3
8.4
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
Address Space Maps..................................................
42
Overview....................................................................... 42
Flash Memory Array...................................................... 42
ID-CFI Address Space .................................................. 42
JEDEC JESD216 Serial Flash
Discoverable Parameters (SFDP) Space. .................... 43
OTP Address Space ..................................................... 43
Registers....................................................................... 44
Data Protection
........................................................... 53
Secure Silicon Region (OTP)........................................ 53
Write Enable Command................................................ 53
Block Protection ............................................................ 54
Advanced Sector Protection ......................................... 55
Commands
.................................................................. 59
Command Set Summary............................................... 60
Identification Commands .............................................. 65
Register Access Commands......................................... 67
Read Memory Array Commands .................................. 76
Program Flash Array Commands ................................. 90
Erase Flash Array Commands...................................... 93
One Time Program Array Commands .......................... 97
Advanced Sector Protection Commands ...................... 98
Reset Commands ....................................................... 102
Embedded Algorithm Performance Tables ................. 103
Hardware Interface
Signal Descriptions
..................................................... 8
Input/Output Summary................................................... 8
Address and Data Configuration.................................... 9
RESET# ......................................................................... 9
Serial Clock (SCK) ......................................................... 9
Chip Select (CS#) .......................................................... 9
Serial Input (SI) / I/O0 .................................................. 10
Serial Output (SO) / I/O1.............................................. 10
Write Protect (WP#) / I/O2 ........................................... 10
Hold (HOLD#) / I/O3 .................................................... 10
Core Voltage Supply (V
CC
) .......................................... 11
Versatile I/O Power Supply (V
IO
) ................................. 11
Supply and Signal Ground (V
SS
) ................................. 11
Not Connected (NC) .................................................... 11
Reserved for Future Use (RFU)................................... 11
Do Not Use (DNU) ....................................................... 11
Block Diagrams............................................................ 12
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Configuration Register Effects on the Interface ...........
Data Protection ............................................................
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Thermal Resistance .....................................................
Operating Ranges........................................................
Power-Up and Power-Down ........................................
DC Characteristics .......................................................
Timing Specifications................................................
Key to Switching Waveforms .......................................
AC Test Conditions ......................................................
Reset............................................................................
SDR AC Characteristics...............................................
DDR AC Characteristics ..............................................
Physical Interface
......................................................
SOIC 16-Lead Package ...............................................
FAB024 24-Ball BGA Package ....................................
FAC024 24-Ball BGA Package ....................................
13
13
14
17
22
22
23
23
23
23
24
26
27
27
27
28
30
33
36
36
38
40
10. Data Integrity
............................................................. 104
10.1 Erase Endurance ........................................................ 104
10.2 Data Retention ............................................................ 104
11. Software Interface Reference
.................................. 105
11.1 Command Summary ................................................... 105
11.2 Serial Flash Discoverable Parameters
(SFDP) Address Map.................................................. 106
11.3 Device ID and Common Flash Interface
(ID-CFI) Address Map................................................. 109
11.4 Registers..................................................................... 124
11.5 Initial Delivery State .................................................... 127
12
Ordering Information
................................................ 128
13. Revision History........................................................
130
Document History Page ....................................................130
Sales, Solutions, and Legal Information .........................133
Worldwide Sales and Design Support ..........................133
Products .......................................................................133
PSoC® Solutions .........................................................133
Cypress Developer Community ....................................133
Technical Support ........................................................133
Document Number: 001-98284 Rev. *N
Page 3 of 133
S25FL512S
1. Overview
1.1 General Description
The Cypress S25FL512S device is a flash nonvolatile memory product using:
MirrorBit technology - that stores two data bits in each memory array transistor
Eclipse architecture - that dramatically improves program and erase performance
65 nm process lithography
This device connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single
I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple
width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for Double Data Rate (DDR) read commands
for SIO, DIO, and QIO that transfer address and read data on both edges of the clock.
The Eclipse architecture features a Page Programming Buffer that allows up to 256 words (512 bytes) to be programmed in one
operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates
supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface,
asynchronous, NOR flash memories while reducing signal count dramatically.
The S25FL512S product offers high densities coupled with the flexibility and fast performance required by a variety of embedded
applications. It is ideal for code shadowing, XIP, and data storage.
1.2 Migration Notes
1.2.1
Features Comparison
The S25FL512S device is command set and footprint compatible with prior generation FL-K and FL-P families.
Table 1. FL Generations Comparison
Parameter
Technology Node
Architecture
Release Date
Density
Bus Width
Supply Voltage
Normal Read Speed (SDR)
Fast Read Speed (SDR)
Dual Read Speed (SDR)
Quad Read Speed (SDR)
Fast Read Speed (DDR)
Dual Read Speed (DDR)
Quad Read Speed (DDR)
Program Buffer Size
Erase Sector Size
Parameter Sector Size
Sector Erase Time (typ.)
Page Programming Time (typ.)
OTP
Advanced Sector Protection
Auto Boot Mode
FL-K
90 nm
Floating Gate
In Production
4 Mb - 128 Mb
x1, x2, x4
2.7 V - 3.6 V
6 MB/s (50 MHz)
13 MB/s (104 MHz)
26 MB/s (104 MHz)
52 MB/s (104 MHz)
—
—
—
256B
4 kB / 32 kB / 64 kB
4 kB
30 ms (4 kB), 150 ms (64 kB)
700 µs (256B)
768B (3 x 256B)
No
No
FL-P
90 nm
MirrorBit
In Production
32 Mb - 256 Mb
x1, x2, x4
2.7 V - 3.6 V
5 MB/s (40 MHz)
13 MB/s (104 MHz)
20 MB/s (80 MHz)
40 MB/s (80 MHz)
—
—
—
256B
64 kB / 256 kB
4 kB
500 ms (64 kB)
1500 µs (256B)
506B
No
No
FL-S
65 nm
MirrorBit Eclipse
In Production
512 Mb
x1, x2, x4
2.7 V - 3.6 V / 1.65 V - 3.6 V V
IO
6 MB/s (50 MHz)
17 MB/s (133 MHz)
26 MB/s (104 MHz)
52 MB/s (104 MHz)
20 MB/s (80 MHz)
40 MB/s (80 MHz)
80 MB/s (80 MHz)
512B
256 kB
—
520 ms (256 kB)
340 µs (512B)
1024B
Yes
Yes
Document Number: 001-98284 Rev. *N
Page 4 of 133
S25FL512S
Table 1. FL Generations Comparison (Continued)
Parameter
Erase Suspend/Resume
Program Suspend/Resume
Operating Temperature
FL-K
Yes
Yes
–40 °C to +85 °C
FL-P
No
No
–40 °C to +85 °C / +105 °C
FL-S
Yes
Yes
–40 °C to +85 °C / +105 °C
Notes
1. 256B program page option only for 128-Mb and 256-Mb density FL-S devices.
2. FL-P column indicates FL129P MIO SPI device (for 128-Mb density).
3. 64 kB sector erase option only for 128-Mb/256-Mb density FL-P and FL-S devices.
4. FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB.
5. Refer to individual data sheets for further details.
1.2.2
1.2.2.1
Known Differences from Prior Generations
Error Reporting
Prior generation FL memories either do not have error status bits or do not set them if program or erase is attempted on a protected
sector. The FL-S family does have error reporting status bits for program and erase operations. These can be set when there is an
internal failure to program or erase or when there is an attempt to program or erase a protected sector. In either case the program or
erase operation did not complete as requested by the command.
1.2.2.2
Secure Silicon Region (OTP)
The size and format (address map) of the One Time Program area is different from prior generations. The method for protecting
each portion of the OTP area is different. For additional details see
Secure Silicon Region (OTP) on page 53.
1.2.2.3
Configuration Register Freeze Bit
The configuration register Freeze bit CR1[0], locks the state of the Block Protection bits as in prior generations. In the FL-S family it
also locks the state of the configuration register TBPARM bit CR1[2], TBPROT bit CR1[5], and the Secure Silicon Region (OTP)
area.
1.2.2.4
Sector Erase Commands
The command for erasing an 8-kbyte area (two 4-kbyte sectors) is not supported.
The command for erasing a 4-kbyte sector is not supported in the 512-Mbit density FL-S device.
The erase command for 64-kbyte sectors is not supported in the 512-Mbit density FL-S device.
1.2.2.5
Deep Power Down
The Deep Power Down (DPD) function is not supported in FL-S family devices.
The legacy DPD (B9h) command code is instead used to enable legacy SPI memory controllers, that can issue the former DPD
command, to access a new bank address register. The bank address register allows SPI memory controllers that do not support
more than 24 bits of address, the ability to provide higher order address bits for commands, as needed to access the larger address
space of the 256-Mbit density FL-S device. For additional information see
Extended Address on page 42.
Document Number: 001-98284 Rev. *N
Page 5 of 133
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