S29AL008D90MAI013 datasheet, PDF

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S29AL008D90MAI013: DescriptionFlash, 512KX16, 90ns, PDSO44, MO-180AAA, SOP-44; Categorystorage storage; File Size2MB，49 Pages; ManufacturerCypress Semiconductor

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S29AL008D90MAI013 Overview

Flash, 512KX16, 90ns, PDSO44, MO-180AAA, SOP-44

S29AL008D90MAI013 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
package instruction	SOP,
Reach Compliance Code	compli
Maximum access time	90 ns
Other features	TOP BOOT BLOCK
Spare memory width	8
startup block	TOP
JESD-30 code	R-PDSO-G44
JESD-609 code	e0
length	28.2 mm
memory density	8388608 bi
Memory IC Type	FLASH
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of terminals	44
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX16
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Programming voltage	3 V
Maximum seat height	2.8 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	13.3 mm

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S29AL008D

8 Mbit (1M x 8-Bit/512 K x 16-Bit), 3 V

Boot Sector Flash

This product has been retired and is not recommended for designs. For new and current designs, S29AL008J supercedes

S29AL008D. This is the factory-recommended migration path. Please refer to the S29AL008J data sheet for specifications and

ordering information.

Distinctive Characteristics

Architectural Advantage



Single Power Supply Operation

– 2.7 to 3.6 volt read and write operations for battery-powered

applications



Manufactured on 200 nm Process Technology

– Compatible with 0.32 µm and 230 nm Am29LV800 devices



Flexible Sector Architecture

– One 16-Kbyte, two 8-Kbyte, one 32-Kbyte, and fifteen 64-Kbyte

sectors (byte mode)

– One 8 Kword, two 4 Kword, one 16-Kword, and fifteen 32-Kword

sectors (word mode)

– Supports full chip erase

– Sector Protection features:

– A hardware method of locking a sector to prevent any program or

erase operations within that sector

– Sectors can be locked in-system or via programming equipment

– Temporary Sector Unprotect feature allows code changes in

previously locked sectors



Unlock Bypass Program Command

– Reduces overall programming time when issuing multiple program

command sequences



Top or Bottom Boot Block Configurations Available



Embedded Algorithms

– Embedded Erase algorithm automatically preprograms and

erases the entire chip or any combination of designated sectors

– Embedded Program algorithm automatically writes and verifies

data at specified addresses



Compatibility with JEDEC Standards

– Pinout and software compatible with single-power supply Flash

– Superior inadvertent write protection

Performance Characteristics



High Performance

– Access times as fast as 55 ns

– Extended temperature range (-40°C to +125°C)



Ultra-low Power Consumption (typical values at 5 MHz)

– 200 nA Automatic Sleep mode current

– 200 nA standby mode current

– 7 mA read current

– 15 mA program/erase current



Data Retention: 20 years typical

– Reliable operation for the life of the system



48-ball FBGA

•



48-pin TSOP



44-pin SO

Software Features



Data# Polling and Toggle Bits

– Provides a software method of detecting program or erase

operation completion



Erase Suspend/Erase Resume

– Suspends an erase operation to read data from, or program data

to, a sector that is not being erased, then resumes the erase

operation

Hardware Features



Ready/Busy# Pin (RY/BY#)

– Provides a hardware method of detecting program or erase cycle

completion



Hardware Reset Pin (RESET#)

– Hardware method to reset the device to reading array data

Cypress Semiconductor Corporation

Document Number: 002-01233 Rev. *A

•

198 Champion Court

Package Option

San Jose

CA 95134-1709

•

408-943-2600

Revised December 09, 2015



Cycling Endurance: 1,000,000 cycles per sector typical

S29AL008D

General Description

The S29AL008D is an 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in

48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. For more information, refer to publication number 21536. The word-wide data

(x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device requires only a single, 3.0 volt V

supply

to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device.

This device is manufactured using Spansion’s 200 nm process technology, and offers all the features and benefits of the

Am29LV800B, which was manufactured using 0.32 µm process technology.

The standard device offers access times of 55, 60, 70, and 90 ns, allowing high speed microprocessors to operate without wait

states. To eliminate bus contention the device contains separate chip enable (CE#), write enable (WE#) and output enable (OE#)

controls.

The

hardware RESET# pin

terminates any operation in progress and resets the internal state machine to reading array data. The

RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system

microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the

automatic sleep mode.

The system can also place the device into the

standby mode.

Power consumption is greatly reduced in

both these modes.

Spansion’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality,

reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling.

The data is programmed using hot electron injection.

Document Number: 002-01233 Rev. *A

The

Erase Suspend

feature enables the user to put erase on hold for any period of time to read data from, or program data to, any

sector that is not selected for erasure. True background erase can thus be achieved.

Hardware data protection

measures include a low V

detector that automatically inhibits write operations during power

transitions. The

hardware sector protection

feature disables both program and erase operations in any combination of the sectors

of memory. This can be achieved in-system or via programming equipment.

The

sector erase architecture

allows memory sectors to be erased and reprogrammed without affecting the data contents of other

sectors. The device is fully erased when shipped from the factory.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7

(Data# Polling) and DQ6 (toggle)

status bits.

After a program or erase cycle is completed, the device is ready to read array data or

accept another command.

Device erasure occurs by executing the erase command sequence. This initiates the

Embedded Erase

algorithm—an internal

algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During

erase, the device automatically times the erase pulse widths and verifies proper cell margin.

Device programming occurs by executing the program command sequence. This initiates the

Embedded Program

algorithm—an

internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The

Unlock Bypass

mode

facilitates faster programming times by requiring only two write cycles to program data instead of four.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard.

Commands are written to

the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine

that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming

and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

The device requires only a

single 3.0 volt power supply

for both read and write functions. Internally generated and regulated

voltages are provided for the program and erase operations.

Page 2 of 49

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