FemtoClock™ Multi-Rate 3.3V LVPECL
Frequency Synthesizer
G
ENERAL
D
ESCRIPTION
The 843034-06 is a general purpose, low phase noise LVPECL
synthesizer which can generate frequencies for a wide variety of
applications. The 843034-06 has a 4:1 input multiplexer from which
the following inputs can be selected: one differential input, one
single-ended input, or one of two crystal oscillators, thus making
the device ideal for frequency translation or frequency generation.
The 843034-06 has dual LVPECL outputs that may be programmed
for ÷2, ÷4 or ÷5 of the VCO frequency. The 843034-06 also supplies
a buffered copy of the reference clock or crystal frequency on the
single-ended REF_OUT pin which can be enabled or disabled
(disabled by default). The output frequency can be programmed
using either a serial or parallel programming interface. This device
supports Spread Spectrum Clocking (SSC) for EMI reduction.
843034-06
DATA SHEET
F
EATURES
•
Dual differential 3.3V LVPECL outputs
•
4:1 Input Mux:
One differential input
One single-ended input
Two crystal oscillator interfaces
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
Output frequency range: 120MHz to 375MHz
•
Crystal input frequency range: 12MHz to 40MHz
•
VCO range: 600MHz to 750MHz
•
Supports Spread Spectrum Clocking (SSC)
•
Parallel or serial interface for programming feedback divider
and output dividers
•
RMS phase jitter at 166.6MHz, using a 22.222MHz crystal
(12kHz to 30MHz): 1.33ps (typical), SSC - Off
•
3.3V supply mode
•
0°C to 75°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
OE_A
Pullup
VCO_SEL
Pullup
XTAL_IN0
OSC
XTAL_OUT0
XTAL_IN1
XTAL_OUT1
OSC
01
00
0
001
÷
2
011
÷
4
100
÷
5
FOUTA0
nFOUTA0
V
CCO_A
V
CCO_B
FOUTB0
nFOUTB0
P
IN
A
SSIGNMENT
CLK
Pullup
nCLK
Pullup/Pulldown
REF_CLK
Pulldown
SEL1
Pulldown
SEL0
Pulldown
OE_B
Pullup
MR
Pulldown
OE_REF
Pulldown
S_LOAD
Pulldown
S_DATA
Pulldown
S_CLOCK
Pulldown
nP_LOAD
Pulldown
10
11
Phase
VCO
Detector
÷
M
1
V
CCO_REF
REF_OUT
TEST
M8:M0
M0:M4 M6:M8 Pulldown, M5 Pullup
NA2:NA0
NA2 Pulldown, NA1:0 Pullup
Configuration
Interface
Logic
843034-06 REVISION B 8/17/15
1
©2015 Integrated Device Technology, Inc.
843034-06 DATA SHEET
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes operation
using a 22.22MHz crystal. Valid PLL loop divider values for differ-
ent crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 6, NOTE 1.
The 843034-06 features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 22.22MHz crystal provides a 22.22MHz phase detector
reference frequency. The VCO of the PLL operates over a range of
600MHz to 750MHz. The output of the M divider is also applied to
the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVPECL output
buffers. The divider provides a 50% output duty cycle.
The 843034-06 supports either serial or parallel programming
modes to program the M feedback divider and N output divider.
Figure 1
shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on the M
and NA inputs are passed directly to the M divider and N output
dividers. On the LOW-to-HIGH transition of the nP_LOAD input,
the data is latched and the M and N dividers remain loaded until
the next LOW transition on nP_LOAD or until a serial event oc-
curs. As a result, the M and NA bits can be hardwired to set the
M divider and NA output divider to a specific default state that
will automatically occur during power-up. The TEST output is
LOW when operating in the parallel input mode. The relationship
between the VCO frequency, the crystal frequency and the M divider
is defined as follows:
fVCO = fxtal x M
The M value and the required values of M0 through M8 are shown
in Table 4B to program the VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock for a 22.22MHz reference
are defined as 26
≤
M
≤
33. The frequency out is defined as follows:
FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and NA output divider when S_LOAD tran-
sitions from LOW-to-HIGH. The M divide and NA output divide values
are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD
is held HIGH, data at the S_DATA input is passed directly to the M
divider and NA output divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and NA bits and
test bits T1 and T0. The internal registers T0 and T1 determine the
state of the TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_Data, Shift Register Output
Output of M divider
Same frequency as FOUTA0
FemtoClock™ Multi-Rate 3.3V LVPECL
Frequency Synthesizer
2
REVISION B 8/17/15
843034-06 DATA SHEET
T
ABLE
1. SSM O
PERATION
SS Bit Pattern
SS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Operation
Mode
off
center
center
center
center
center
center
center
off
down
down
down
down
down
down
down
%
0
±0.25
±0.25
±0.85
±0.85
±1.45
±1.45
±1.7
0
-0.25
-0.25
-0.75
-0.75
-1.25
-1.25
-1.5
NOTE: SS modulation frequency is approximately 32kHz using
reference frequency of 22.22MHz, providing a VCO frequency of
666.66MHz.
S
PREAD
S
PECTRUM
M
ODULATION
The 843034-06 offers the option of a spread spectrum modulated
output clock. The spread spectrum is controlled via 4 bits in the
serial bit stream. These four bits configure the SSM to be enabled
and the amount of spread modulation to be selected. See
Table
1
for the definition of the four bits. The four bits are added at the
beginning of the serial data stream and are labeled SS3, SS2, SS1
and SS0. The initial state of SS3, SS2, SS1 and SS0 is 0, 0, 0, 0
which places the 843034-06 in the mode of spread spectrum off.
Additionally, a parallel load will result in spread spectrum modulation
being off. The 843034-06 offers down-spread or center-spread using
triangle-wave modulation. NOTE: PLL operation not guaranteed for
M >31 when using center spread.
P
OWER
-U
P
O
PERATION
The 843034-06 has internal power–up reset circuitry that initiates
the phase lock loop to automatically acquire lock on power-up. On
power-up the M/N values for the feedback and output dividers will be
acquired from the M and N pins if nP_Load is held Low. If nP_Load
is High during power-up, M/N values are indeterminate. The M/N
values may be changed by either changing the values on the M/N
pins when nP_LOAD is low or with a serial load when nP_LOAD is
high and S_LOAD is low.
MR P
IN
O
PERATION
Any time there is a change in the input frequency, either due to an
external change or a change in the SEL pins, the MR pin must go
high and low to relock to the new input frequency. A change in the
M feedback divider by either a serial or parallel load will also cause
a relock to the new input frequency.
REVISION B 8/17/15
3
FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer
843034-06 DATA SHEET
T
ABLE
2. P
IN
D
ESCRIPTIONS
Number
1, 41, 42,
43, 44, 45,
47, 48
2, 3, 4
5
6
7
8, 14
9, 10
11
12, 24
13
15, 16
17
18, 19
20
21
22
23
Name
M8, M0, M1,
M2, M3,
M4, M6, M7
RESERVED
OE_REF
OE_A
OE_B
V
CC
NA0, NA1
NA2
V
EE
TEST
FOUTA0, nFOU-
TA0
V
CCO_A
FOUTB0,
nFOUTB0
V
CCO_B
REF_OUT
V
CCO_REF
nc
Input
Reserve
Input
Input
Input
Power
Input
Input
Power
Output
Output
Power
Output
Power
Output
Power
Unused
Pullup
Pulldown
Pullup
Pullup
Type
Pulldown
Description
M divider input. Data latched on LOW-to-HIGH transition of nP_LOAD
input. LVCMOS/LVTTL interface levels.
Reserved pins. Do not connect.
Output enable. Controls enabling and disabling of REF_OUT output.
LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTA0, nFOUTA0
outputs. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTB0, nFOUTB0
outputs. LVCMOS/LVTTL interface levels.
Core supply pins.
Determines output divider value as defined in Table 4C,
Pulldown Function Table. LVCMOS/LVTTL interface levels.
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode.
LVCMOS/LVTTL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Output supply pin for FOUTA0, nFOUTA0.
Differential output for the synthesizer. LVPECL interface levels.
Output supply pin for FOUTB0, nFOUTB0.
Reference clock output. LVCMOS/LVTTL interface levels.
Output supply pin for REF_OUT output.
No connect.
Active High Master Reset. When logic HIGH, forces the internal PLL to
a reset condition which holds the VCO at the minumum value. When
logic LOW, the internal dividers and the outputs are enabled. Assertion
of MR does not affect loaded M, N, S and T values. LVCMOS/LVTTL
interface levels.
Clocks in serial data present at S_DATA input into the shift register on
the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers. LVC-
MOS/LVTTL interface levels.
Analog supply pin.
Pulldown Clock select inputs. LVCMOS/LVTTL interface levels.
Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN0 is the input,
XTAL_OUT0 is the output.
Crystal oscillator interface. XTAL_IN1 is the input,
XTAL_OUT1 is the output.
25
MR
Input
Pulldown
26
27
28
29
30, 31
32
33, 34
35, 36
S_CLOCK
S_DATA
S_LOAD
V
CCA
SEL0, SEL1
REF_CLK
XTAL_IN0,
XTAL_OUT0
XTAL_IN1,
XTAL_OUT1
Input
Input
Input
Power
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Continued on next page...
FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer
4
REVISION B 8/17/15
843034-06 DATA SHEET
T
ABLE
2. P
IN
D
ESCRIPTIONS
,
CONTINUED
Number
37
38
39
40
46
Name
CLK
nCLK
nP_LOAD
VCO_SEL
M5
Input
Input
Input
Input
Input
Type
Description
Pulldown Non-inverting differential clock input.
Pullup/
Inverting differential clock input.V
CC
/2 default when left floating.
Pulldown
Parallel load input. Determines when data present at M8:M0 is loaded into
Pulldown M divider, and when data present at NA2:NA0 is loaded into the N output
dividers. LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS/LVTTL interface levels.
M divider input. Data latched on LOW-to-HIGH transition of nP_LOAD input.
Pullup
LVCMOS/LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 3, Pin Characteristics, for typical values.
T
ABLE
3. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
REF_OUT
5
Test Conditions
Minimum
Typical
4
51
51
7
12
Maximum
Units
pF
kΩ
kΩ
Ω
REVISION B 8/17/15
5
FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer
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