8SLVD1212ANLGI8 datasheet, PDF

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8SLVD1212ANLGI8: DescriptionVFQFPN-40, Reel; Categorylogic logic; File Size2MB，20 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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8SLVD1212ANLGI8 Overview

VFQFPN-40, Reel

8SLVD1212ANLGI8 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	VFQFPN
package instruction	HVQCCN,
Contacts	40
Manufacturer packaging code	NLG40P2
Reach Compliance Code	compli
Samacsys Descripti	VFQFP-N 6.0 X 6.0 X 0.9 MM - NO LEAD
series	8SLVD
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N40
JESD-609 code	e3
length	6 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	40
Actual output times	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	0.5 ns
Same Edge Skew-Max（tskwd）	0.04 ns
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	6 mm

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1:12, LVDS Output Fanout

8SLVD1212

Datasheet

Description

The 8SLVD1212 is a high-performance differential LVDS fanout

buffer. The device is designed for the fanout of high-frequency,

very low additive phase-noise clock and data signals.

The 8SLVD1212 is characterized to operate from a 2.5V power

supply. Guaranteed output-to-output and part-to-part skew

characteristics make the device ideal for clock distribution

applications that demand well-defined performance and

repeatability.

Two selectable differential inputs and twelve low skew outputs are

available. The integrated bias voltage reference enables easy

interfacing of single-ended signals to the device inputs.

The 8SLVD1212 is optimized for low power consumption and low

additive phase noise.

Features

▪

Twelve low skew, low additive jitter LVDS output pairs

▪

Two selectable, differential clock input pairs

▪

Differential PCLK, nPCLK pairs can accept the following

differential input levels: LVDS, LVPECL, CML

▪

Maximum input clock frequency: 2GHz (maximum)

▪

LVCMOS/LVTTL interface levels for the control input select

pins

▪

Output skew: 40ps (maximum)

▪

Propagation delay: 310ps (typical)

▪

Low additive phase jitter, RMS; f

REF

= 156.25MHz,

10kHz to 20MHz: 77fs (typical)

▪

Device current consumption (I

): 213mA (maximum)

▪

2.5V supply voltage

▪

Lead-free (RoHS 6), 6



6 mm, 40-VFQFN packaging

▪

-40°C to 85°C ambient operating temperature

Block Diagram

8SLVD1212

REF0

Voltage

Reference

nQ0

nQ1

nQ2

nQ3

GND

REF

PCLK0

nPCLK0

nQ4

nQ5

nQ6

PCLK1

nPCLK1

GND

nQ7

nQ8

nQ9

Q10

nQ10

Q11

nQ11

SEL

GND

REF1

Voltage

Reference

February 2, 2021

8SLVD1212 Datasheet

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin Descriptions and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Additive Phase Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Parameter Measurement Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Recommendations for Unused Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Wiring the Differential Input to Accept Single-Ended Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.5V LVPECL Clock Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

LVDS Driver Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

VFQFN EPAD Thermal Release Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power Considerations (8SLVD1212A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reliability Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

February 2, 2021

8SLVD1212ANLGI8 Related Products

	8SLVD1212ANLGI8	8SLVD1212ANLGI	8SLVD1212ANLGI/W	8SLVD1212NLGI	8SLVD1212NLGI8
Description	VFQFPN-40, Reel	VFQFPN-40, Tray	VFQFPN-40, Reel	VFQFPN-40, Tray	VFQFPN-40, Reel
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	VFQFPN	VFQFPN	VFQFPN	VFQFPN	VFQFPN
package instruction	HVQCCN,	HVQCCN,	HVQCCN,	HVQCCN, LCC40,.24SQ,20	HVQCCN, LCC40,.24SQ,20
Contacts	40	40	40	40	40
Manufacturer packaging code	NLG40P2	NLG40P2	NLG40P2	NLG40P2	NLG40P2
Reach Compliance Code	compli	compli	compli	compli	compli
series	8SLVD	8SLVD	8SLVD	8SLVD	8SLVD
Input adjustment	DIFFERENTIAL MUX	DIFFERENTIAL MUX	DIFFERENTIAL MUX	DIFFERENTIAL MUX	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N40	S-XQCC-N40	S-XQCC-N40	S-XQCC-N40	S-XQCC-N40
JESD-609 code	e3	e3	e3	e3	e3
length	6 mm	6 mm	6 mm	6 mm	6 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	3	3	3	3	3
Number of functions	1	1	1	1	1
Number of terminals	40	40	40	40	40
Actual output times	24	24	24	24	24
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN	HVQCCN	HVQCCN	HVQCCN
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260	260	260	260
propagation delay (tpd)	0.5 ns	0.5 ns	0.5 ns	0.5 ns	0.5 ns
Same Edge Skew-Max（tskwd）	0.04 ns	0.04 ns	0.04 ns	0.045 ns	0.045 ns
Maximum seat height	1 mm	1 mm	1 mm	1 mm	1 mm
Maximum supply voltage (Vsup)	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin (Sn)	Tin (Sn)	Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.65 mm	0.65 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	6 mm	6 mm	6 mm	6 mm	6 mm
Samacsys Descripti	VFQFP-N 6.0 X 6.0 X 0.9 MM - NO LEAD	VFQFP-N 6.0 X 6.0 X 0.9 MM - NO LEAD	VFQFP-N 6.0 X 6.0 X 0.9 MM - NO LEAD	-	-

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