ADVANCE D COM P ON E NTS PACKAG I NG
128 Megabit CMOS DDR SDRAM
DPDD32MX4RSAY5
DESCRIPTION:
The Memory Stack™ series is a family of interchangeable memory devices. The 128 Mb, CMOS DDR Synchronous DRAM
assembly utilizes the space saving LP-Stack™ technology to increase memory density. This stack is constructed with two 64Mb
(16M x 4) DDR SDRAMs.
PINOUT DIAGRAM
This 128 Mb LP-Stack™, has been designed to fit in the
same footprint as the 64Mb (16M x 4) DDR SDRAM
66 VSS
VDD
1
NC
65 NC
2
TSOPII monolithic. This allows system upgrade without
64 VSSQ
VDDQ
3
electrical or mechanical redesign, providing an alternative
63 NC
NC
4
low cost memory solution.
62 DQ3
DQ0
5
1
FEATURES:
• Electrical characteristics meet semiconductor
manufacturers’ datasheet
• Memory organization:
(2) 64Mb memory devices. Each device arranged
as 16M x 4 bits (4M x 4 bits x 4 banks)
• Memory stack organization:
32M x 4 bits (8M x 4 bits x 4 banks)
• JEDEC approved, 2 Rank stack pinout and footprint
(with 2 CSs and 2 CKEs)
• Optimized for RDIMMs
• IPC-A-610, class 2, manufacturing standards
• Lead free manufacturing process
• Package: 66-Pin TSOPII stack
A0-A11
R
PIN NAMES
Row Address:
Column Address:
Auto Precharge
Data In/Data Out
Chip Selects
E
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
DNU
NC
WE
CAS
RAS
CS0
CS1
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
(TOP VIEW)
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
DNU
VREF
VSS
DM
CK
CK
CKE0
CKE1
NC
A11
A9
A8
A7
A6
A5
A4
VSS
L
I
M
I
N
A
R
Y
A0-A11
A0-A9
BA0, BA1
A10/AP
DQ0-DQ3
CAS
CS0, CS1
RAS
WE
CK, CK
CKE0, CKE1
DQS
DM
V
DD
V
SS
V
DDQ
V
SSQ
VREF
NC
DNU
30A222-00
REV. H 2/03
Bank Select Address
FUNCTIONAL BLOCK DIAGRAM
CS1
CKE1
CS0
CKE0
RAS
CAS
WE
CK
CK
VREF
DQS
DM
A0-A11
BA0-BA1
P
Row Address Strobe
Data Write Enable
Differential Clock Inputs
Clock Enables
Data Strobe
Data Mask
Power Supply
Ground
DQ Power Supply
DQ Ground
SSTL_2 Reference Voltage
No Connect
Do Not Use
64 Mb DDR SDRAM
(4M x 4 bits x 4 banks)
(4 Meg x 4 Bits x 4 Banks)
Column Address Strobe
DQ0-DQ3
This document contains information on a product presently under development at DPAC Technologies.
DPAC reserves the right to change products or specifications herein without prior notice.
1
128 Megabit CMOS DDR SDRAM
DPDD32MX4RSAY5
ORDERING INFORMATION
DP
PREFIX
DD
TYPE
32M
MEMORY
DEPTH
X
DESIG
4
MEMORY
WIDTH
R
DESIG
S
I/O TYPE
A
DEVICE
WIDTH
Y5
PACKAGE
- DP - XX
SUPPLIER
MFR ID
XX
CYCLE
TIME
XX
CAS
LATENCY
15
20
25
30
60
70
75
08
10
CAS LATENCY 1.5
CAS LATENCY 2.0
CAS LATENCY 2.5
CAS LATENCY 3.0
6ns (166MHz)
7ns (143MHz)
7.5ns (133MHz)
8ns (125MHz)
10ns (100MHz)
MANUFACTURER CODE*
SUPPLIER CODE*
STACKABLE TSOP
x4 MEMORY BASED
SSTL INPUTS/OUTPUTS
64 MEGABIT BASED
MEMORY MODULE WITHOUT SUPPORT LOGIC
DOUBLE DATA RATE SYNCHRONOUS DRAM
Y
* Contact your sales representative for supplier and manufacturer codes.
NOTES:
1. AC Parameters of base memory are unchanged from device manufacturers’ specifications.
2.
3.
4.
DC Parameters may be affected by stacking. Please refer to application note 53A004-00 for further information.
For assembly and inspection procedures, refer to application note 53A001-00.
Maximum reflow temperature recommendation is 215°C.
I
N
A
R
MECHANICAL DIAGRAM
M
PIN 1
INDEX
TOP VIEW
1
SIDE VIEW
BOTTOM VIEW
E
L
I
P
R
.891 MAX.
[22.63 MAX.]
.0256 [.65]
TYP
.015 [.18]
TYP
.102 MAX [2.59 MAX]
END VIEW
END VIEWDETAIL
.502±.008
[12.75±.20]
COPLANARITY:
.004 [.10] from seating plane
Inch [mm]
.463 [11.76] TYP
Lead Toe-to-Toe per device datasheet
30A222-00
REV. H 2/03
DPAC Technologies
Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841
Tel
714 898 0007
Fax
714 897 1772
www.dpactech.com Nasdaq: DPAC
2
©2003 DPAC Technologies, all rights reserved. DPAC Technologies™, Memory Stack™, System Stack™, LP-Stack™, CS-Stack™ are trademarks of DPAC Technologies Corp.
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