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V54C3128404VBLF6

Description
Synchronous DRAM, 32MX4, 5.4ns, CMOS, PBGA60, LEAD FREE, MO-210, FBGA-60
Categorystorage    storage   
File Size694KB,54 Pages
ManufacturerProMOS Technologies Inc
Environmental Compliance  
Download Datasheet Parametric View All

V54C3128404VBLF6 Overview

Synchronous DRAM, 32MX4, 5.4ns, CMOS, PBGA60, LEAD FREE, MO-210, FBGA-60

V54C3128404VBLF6 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerProMOS Technologies Inc
Parts packaging codeBGA
package instructionTFBGA, BGA60,8X15,32
Contacts60
Reach Compliance Codecompli
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time5.4 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)166 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PBGA-B60
length13 mm
memory density134217728 bi
Memory IC TypeSYNCHRONOUS DRAM
memory width4
Number of functions1
Number of ports1
Number of terminals60
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32MX4
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Encapsulate equivalent codeBGA60,8X15,32
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
refresh cycle4096
Maximum seat height1.2 mm
self refreshYES
Continuous burst length1,2,4,8
Maximum standby current0.001 A
Maximum slew rate0.27 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width8 mm
V54C3128(16/80/40)4VB
128Mbit SDRAM
3.3 VOLT, TSOP II / FBGA
8M X 16, 16M X 8, 32M X 4
6
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
Features
4 banks x 2Mbit x 16 organization
4 banks x 4Mbit x 8 organization
4 banks x 8Mbit x 4 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8, and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 60-ball FBGA and 54 Pin TSOPII
LVTTL Interface
Single +3.3 V
±0.3
V Power Supply
Description
The V54C3128(16/80/40)4VB is a four bank Syn-
chronous DRAM organized as 4 banks x 2Mbit x 16,
4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4. The
V54C3128(16/80/40)4VB achieves high speed data
transfer rates up to 166 MHz by employing a chip
architecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
T/S
Access Time (ns)
6
Power
8PC
7PC
7
Std.
L
Temperature
Mark
Blank
V54C3128(16/80/40)4VB Rev. 1.2 January 2005
1
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