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LF48212JC20

Description
Mixer, 12-Bit, CMOS, PQCC68, PLASTIC, LCC-68
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size75KB,9 Pages
ManufacturerLOGIC Devices
Websitehttp://www.logicdevices.com/
Download Datasheet Parametric View All

LF48212JC20 Overview

Mixer, 12-Bit, CMOS, PQCC68, PLASTIC, LCC-68

LF48212JC20 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerLOGIC Devices
Parts packaging codeLCC
package instructionQCCJ,
Contacts68
Reach Compliance Codecompli
ECCN code3A001.A.3
boundary scanNO
maximum clock frequency50 MHz
External data bus width12
JESD-30 codeS-PQCC-J68
JESD-609 codee0
length24.2316 mm
low power modeNO
Humidity sensitivity level3
Number of terminals68
Maximum operating temperature70 °C
Minimum operating temperature
Output data bus width13
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum slew rate120 mA
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width24.2316 mm
uPs/uCs/peripheral integrated circuit typeDSP PERIPHERAL, MIXER
LF48212
DEVICES INCORPORATED
12 x 12-bit Alpha Mixer
LF48212
DEVICES INCORPORATED
12 x 12-bit Alpha Mixer
DESCRIPTION
The LF48212 is a high-speed video
alpha mixer capable of mixing video
signals at real-time video rates. It
takes two 12-bit video signals and
mixes them together using an alpha
mix factor. Alpha determines the
weighting that each video signal
receives during the mix operation.
The input video data can be in either
unsigned or two’s complement
format, but both inputs must be in the
same format. Independently con-
trolled programmable delay stages are
provided for the input and control
signals to allow for allignment of
input data if necessary. The delay
stages can be programmed to have
from 0 to 7 delays. The 13-bit output
of the alpha mixer is registered with
three-state drivers and may be
rounded to 8, 10, 12, or 13-bits.
FEATURES
u
50 MHz Data and Computation
Rate
u
Two’s Complement or Unsigned
Operands
u
On-board Programmable Delay
Stages
u
Programmable Output Rounding
u
Replaces Harris HSP48212
u
Package Styles Available:
• 68-pin PLCC, J-Lead
• 64-pin PQFP
LF48212 B
LOCK
D
IAGRAM
α
11-0
12
DINA
11-0
12
DINB
11-0
12
BYPASS
DEL
LD
DELAY CONTROL
REGISTER
15
0-7
0-7
0-7
FORMAT
FORMAT
α
CLK
MIXEN
OE
1.0 –
α
ADJUST
TC
0-7
4
FORMAT
RND
1-0
0-7
2
4
13
NOTE: NUMBERS IN REGISTERS INDICATE
NUMBER OF PIPELINE DELAYS.
DOUT
12-0
Video Imaging Products
1
08/16/2000–LDS.48212-F
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