3.0 Pin Descriptions and Configuration ............................................................................................................................................... 10
4.0 Power Connections ....................................................................................................................................................................... 16
5.0 USB Device Controller .................................................................................................................................................................. 17
10.0 One Time Programmable (OTP) Memory ................................................................................................................................. 121
12.0 Clocks and Power management (CPM) .................................................................................................................................... 124
13.0 Power Management Event (PME) Operation ............................................................................................................................ 134
16.0 Package Information ................................................................................................................................................................. 237
17.0 Revision History ........................................................................................................................................................................ 240
2015 - 2017 Microchip Technology Inc.
DS00002123D-page 3
LAN7801
1.0
1.1
PREFACE
General Terms
GENERAL TERMS
Description
10 Mbps Ethernet, IEEE 802.3 compliant
100 Mbps Fast Ethernet, IEEE802.3u compliant
100 Mbps Fast Ethernet, IEEE802.3ab compliant
Analog-to-Digital Converter
Analog Front End
Address Logic Resolution
Auto-Negotiation
Always on Always Connected
Address Resolution Protocol
Best Effort Latency Tolerance
Baseline Wander
8 bits
Clocks and Power Management
Carrier Sense Multiple Access/Collision Detect
Control and Status Registers
Counter
Destination Address
32 bits
Embedded Controller
Energy Efficient Ethernet
USB Endpoint
EEPROM Controller
Frame Check Sequence - The extra checksum characters added to the end of an
Ethernet frame, used for error detection and correction.
FIFO Controller
First In First Out buffer
Full Speed
Finite State Machine
Firmware
Gigabit Media Independent Interface
General Purpose I/O
Gigabit Ethernet Physical Layer
External system (Includes processor, application software, etc.)
High Speed
Hardware. Refers to function implemented by digital logic.
Internet Group Management Protocol
Refers to data input to the device from the host
Linear Drop-Out Regulator
This type of status bit is set whenever the condition that it represents is asserted. The
bit remains set until the condition is no longer true and the status bit is cleared by writ-
ing a zero.
TABLE 1-1:
Term
10BASE-T
100BASE-TX
1000BASE-T
ADC
AFE
ALR
AN
AOAC
ARP
BELT
BLW
Byte
CPM
CSMA/CD
CSR
CTR
DA
DWORD
EC
EEE
EP
EPC
FCS
FCT
FIFO
FS
FSM
FW
GMII
GPIO
GPHY
Host
HS
HW
IGMP
Inbound
LDO
Level-Triggered Sticky Bit
DS00002123D-page 4
2015 - 2017 Microchip Technology Inc.
LAN7801
TABLE 1-1:
Term
LFPS
LFSR
LPM
lsb
LSB
LTM
MAC
MDI
MDIX
MEF
MII
MIIM
MIL
MLD
MLT-3
Low Frequency Periodic Signal
Linear Feedback Shift Register
Link Power Management
Least Significant Bit
Least Significant Byte
Latency Tolerance Messaging
Media Access Controller
Medium Dependent Interface
Media Dependent Interface with Crossover
Multiple Ethernet Frames
Media Independent Interface
Media Independent Interface Management
MAC Interface Layer
Multicast Listening Discovery
Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a
change in the logic level represents a code bit “1” and the logic output remaining at the
same level represents a code bit “0”.
Most Significant Bit
Most Significant Byte
Non Return to Zero Inverted. This encoding method inverts the signal for a “1” and
leaves the signal unchanged for a “0”
Not Applicable
No Connect
One Time Programmable
Organizationally Unique Identifier
Refers to data output from the device to the host
Physical Coding Sublayer
Physical Layer
Parallel In Serial Out
Phase Locked Loop
Physical Medium Dependent
Power Management Event
Power Management IC
Power on Reset
Precision Time Protocol
64 bits
Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaran-
teed when reading reserved bits. Unless otherwise noted, do not read or write to
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[img]http://www.fpga4fun.com/images/CrossClockDomain.task.gif[/img]
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Microcontroller MCU
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