ZL30163
Network Synchronization Clock Translator
Data Sheet
March 2015
Features
•
Fully compliant SEC (G.813) , EEC (G.8262) and
Stratum 3E flexible rate conversion digital phase
locked loop (DPLL)
Two programmable DPLLs/Numerically Controlled
Oscillators (NCOs) synchronize to any clock rate
from 1 Hz to 750 MHz
Four programmable synthesizers generate any
clock rate from 1 Hz to 750 MHz with maximum
jitter below 0.62 ps RMS
Flexible two-stage architecture translates between
arbitrary data rates, line coding rates and FEC
rates
DPLLs filter jitter from 0.1 mHz up to 1 kHz
Automatic hitless reference switching and digital
holdover on reference fail
Nine input references configurable as single ended
or differential and two single ended input
references
Any input reference can be fed with sync (frame
pulse) or clock
•
Ordering Information
ZL30163GDG2 144 Pin LBGA
Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C
Package Size: 13 x 13 mm
Trays
•
•
•
•
•
•
Programmable DPLLs can synchronize to sync
pulse and sync pulse/clock pair
Eight LVPECL outputs and eight LVCMOS outputs
Operates from a single crystal resonator or clock
oscillator
Customer defined default device configuration
available via OTP (One Time Programmable)
memory, including input/output frequencies
Dynamically configurable via SPI/I2C interface
and volatile configuration registers
•
•
•
•
•
Figure 1 - Functional Block Diagram
1
Microsemi Corporation
Copyright 2015, Microsemi Corporation. All Rights Reserved.
ZL30163
Applications
•
•
•
SyncE/SONET/SDH Timing Cards
Synchronous Ethernet, 10 GBASE-R and 10 GBASE-W
SONET/SDH, Fibre Channel, XAUI
Data Sheet
2
Zarlink Semiconductor Inc.
ZL30163
Change History
Below are the changes from the September 2014 issue to the March 2015 issue:
Page
1
12
18
19
33
34
98
103
144
198
Item
Added Features bullet
GPIO pin descriptions
Precise Frequency Monitor (PFM)
Guard Soak Timer (GST)
Figure 14 "Typical Power-Up Reset and
Configuration Circuit"
5.1, “ZL30163 Configuration programming“
Register Name: phasemem_limit_ref0
Register Name: page_sel_register
Register Name: dpll0_df_offset
13.0, “Package Markings“
Change
Data Sheet
Included availability of customer defined default
configurations
Updated GPIO[5:6] power-up settings
Clarified PFM measurement interval
Correctd GST description
Updated Figure 14 for GPIO5 and 6 at power-up
Added section 5.1
Corrected 1ms phase memory limit example.
Added description for page 5 registers (0x280-
0x2FF)
Correct the f_out equation in the register
description
Added section 13.0 for package markings
Below are the changes from the February 2014 issue to the September 2014 issue:
Page
195
Item
Lock Time
Change
Changed maximum lock time for a bandwidth of
0.1 Hz and PSL of 0.885 microseconds/s from 20
seconds to 50 seconds. Changed maximum lock
time for a bandwidth of 3.6Hz and PSL of 7.5
microseconds/s from 30 seconds to 50 seconds.
Below are the changes from the January 2014 issue to the February 2014 issue:
Page
1
23
53
Item
Features
Frequency Synthesis Engine
Register Map
Change
Added Stratum 3E compliance to feature list
Added paragraph to match note 2 from register
0x1BA:0x1BB register description
Added Basic Procedure for Refreshing Latest
Device Status from Sticky Read (StickyR)
Registers when using an
Interrupt Handler (event or polling)
Added a note to the register description for the
quadratrue phase shift
Removed parameter T
REFD
163
188
Quadrature Phase Shift
Input to Output Timing
3
Microsemi Corporation
ZL30163
Page
188
188
Item
Input to Output Timing
Input to Output Timing
Change
Added parameter T
HP_DIFF_REFD
Data Sheet
Updated figure 28 and figure 29 to show ref<10:0>
instead of ref<3:0>
Below are the changes from the October 2013 issue to the January 2014 issue:
Page
1
Item
Document status
Change
Moved from preliminary to released
Below are the changes from the September 2013 issue to the October 2013 issue:
Page
54
68
Item
Register Summary: hw_rev_reg
Register Name: hw_rev_reg
Change
Updated default value
Updated default value
Below are the changes from the May 2013 issue to the September 2013 issue:
Page
18
52
61
94
135
148
194
Register Summary: dpll0_pbo_time_out
Register Name: pfm_limit_ref1_0
Register Name: dpll1_mode_refsel
Register Name: synth0_freq_multiple
Section 10.1, “Output Clocks Jitter Generation“
Item
Precise Frequency Monitor (PFM)
Change
Added note about non-integer frequencies
Updated heading title
Corrected description of register
Added note about non-integer frequencies
Corrected bit field length of DPLL1_mode
Added note
Updated table titles for clarity
4
Microsemi Corporation
ZL30163
Data Sheet
Table of Contents
1.0 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.0 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Input Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Input Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 Digital Phase Locked Loop (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3.1 DPLL General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3.2 DPLL Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.3 DPLL Rate Conversion Function and FEC Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3.4 DPLL Input to Output and Output to Output Phase Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4 Frequency Synthesis Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5 Dividers and Skew Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6 Output Clocks Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.7 Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.8 Input Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.9 Master Clock Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.10 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.11 Power Up/Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.12 Power Supply Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.13 Reset and Configuration Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.0 Configuration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1 ZL30163 Configuration programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.1 Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.2 Custom OTP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.3 SPI/I2C Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2 Registers Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2.1 Input Reference Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2.2 DPLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.3 Output Multiplexer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.4 Synthesizer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.5 Output Dividers and Output Phase Offset (skew) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.6 Output Drivers Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3 GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.1 GPIO Indication and Control Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.4 State Control and Reference Switch Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.4.1 Un-managed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.4.2 Managed (Manual) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.5 Reference/Sync Pairing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.0 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.1 Least Significant Bit (LSb) First Transmission Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.2 Most Significant Bit (MSb) First Transmission Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.3 SPI Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.2 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.0 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.0 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
10.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
10.1 Output Clocks Jitter Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
10.2 DPLL Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
5
Microsemi Corporation
京公网安备 11010802033920号
EEWORLD
