Features
•
Low Voltage and Standard Voltage Operation
– 5.0 (V
CC
= 4.5V to 5.5V)
– 2.7 (V
CC
= 2.7V to 5.5V)
– 2.5 (V
CC
= 2.5V to 5.5V)
– 1.8 (V
CC
= 1.8V to 5.5V)
Internally Organized 128 x 8
2-Wire Serial Interface
Bidirectional Data Transfer Protocol
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
4-Byte Page Write Mode
Self-Timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: >3000V
Automotive Grade and Extended Temperature Devices Available
8-Pin PDIP, 8-Pin MSOP, 8-Pin TSSOP and 8-Pin JEDEC SOIC Packages
•
•
•
•
•
•
•
2-Wire Serial
EEPROM
1K (128 x 8)
•
•
Description
The AT24C01 provides 1024 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 128 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low power
and low voltage operation are essential. The AT24C01 is available in space saving
8-pin PDIP, 8-pin MSOP, 8-pin TSSOP, and 8-pin JEDEC SOIC packages and is
accessed via a 2-wire serial interface. In addition, the entire family is available in 5.0V
(4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) ver-
sions.
AT24C01
Pin Configurations
Pin Name
NC
SDA
SCL
Test
Function
No Connect
Serial Data
Serial Clock Input
Test Input (GND or V
CC
)
NC
NC
NC
GND
1
2
3
4
8-Pin MSOP
8-Pin TSSOP
8
7
6
5
VCC
TEST
SCL
SDA
2-Wire, 1K
Serial EEPROM
8-Pin PDIP
NC
NC
NC
GND
1
2
3
4
8
7
6
5
VCC
TEST
SCL
SDA
NC
NC
NC
GND
8-Pin SOIC
1
2
3
4
8
7
6
5
VCC
TEST
SCL
SDA
Rev. 0134C–07/98
1
Absolute Maximum Ratings*
Operating Temperature .................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage........................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Block Diagram
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bidirectional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open
collector devices.
Memory Organization
AT24C01, 1K SERIAL EEPROM:
Internally organized with
128 pages of 1 byte each. The 1K requires a 7-bit data
word address for random word addressing.
2
AT24C01
AT24C01
Pin Capacitance
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +1.8V.
Symbol
C
I/O
C
IN
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
Max
8
6
Units
pF
pF
Condition
V
I/O
= 0V
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AI
= -40°C to +85°C, V
CC
= +1.8V to +5.5V, T
AC
= 0°C to +70°C,
V
CC
= +1.8V to +5.5V (unless otherwise noted).
Symbol
V
CC1
V
CC2
V
CC3
V
CC4
I
CC
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note:
Parameter
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current V
CC
= 5.0V
Supply Current V
CC
= 5.0V
Standby Current V
CC
= 1.8V
Standby Current V
CC
= 2.5V
Standby Current V
CC
= 2.7V
Standby Current V
CC
= 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level
(1)
Input High Level
(1)
Output Low Level V
CC
= 3.0V
Output Low Level V
CC
= 1.8V
I
OL
= 2.1 mA
I
OL
= 0.15 mA
READ at 100 KHz
WRITE at 100 KHz
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
OUT
= V
CC
or V
SS
-0.6
V
CC
×
0.7
Test Condition
Min
1.8
2.5
2.7
4.5
0.4
2.0
0.6
1.4
1.6
8.0
0.10
0.05
Typ
Max
5.5
5.5
5.5
5.5
1.0
3.0
3.0
4.0
4.0
18.0
3.0
3.0
V
CC
×
0.3
V
CC
+ 0.5
0.4
0.2
Units
V
V
V
V
mA
mA
µA
µA
µA
µA
µA
µA
V
V
V
V
1. V
IL
min and V
IH
max are reference only and are not tested.
3
AC Characteristics
Applicable over recommended operating range from T
A
= -40°C to +85°C, V
CC
= +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
2.7-, 2.5-, 1.8-volt
Symbol
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
(1)
Note:
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
(1)
Clock Low to Data Out Valid
Time the bus must be free before a new
transmission can start
(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time
(1)
Inputs Fall Time
(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Page Mode
1M
4.7
100
10
1M
0.1
4.7
4.0
4.7
0
200
1.0
300
0.6
50
10
4.7
4.0
100
4.5
0.1
1.2
0.6
0.6
0
100
0.3
300
Min
Max
100
1.2
0.6
50
0.9
Min
5.0-volt
Max
400
Units
KHz
µs
µs
ns
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write
Cycles
1. This parameter is characterized and is not 100% tested.
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as
defined below.
START CONDITION:
A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
STOP CONDITION:
A low-to-high transition of SDA with
SCL high is a stop condition which terminates all communi-
cations. After a read sequence, the stop command will
place the EEPROM in a standby power mode (refer to Start
and Stop Definition timing diagram).
ACKNOWLEDGE:
All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
Any device on the system bus receiving data (when com-
municating with the EEPROM) must pull the SDA bus low
to acknowledge that it has successfully received each
word. This must happen during the ninth clock cycle after
each word received and after all other system devices have
freed the SDA bus. The EEPROM will likewise acknowl-
edge by pulling SDA low after receiving each address or
data word (refer to Acknowledge Response from Receiver
timing diagram).
STANDBY MODE:
The AT24C01 features a low power
standby mode which is enabled: (a) upon power-up and (b)
after the receipt of the STOP bit and the completion of any
internal operations.
MEMORY RESET:
After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle
while SCL is high and then (c) create a start condition as
SDA is high.
4
AT24C01
AT24C01
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT
WORD n
ACK
t
WR
STOP
CONDITION
(1)
START
CONDITION
Note:
1.
The write cycle time t
WR
is the time from a valid stop condition of a write sequence to the end of the internal clear/write
cycle.
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