MT8VDDT6464AY-26AXX datasheet, PDF

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MT8VDDT6464AY-26AXX: DescriptionDDR DRAM Module, 64MX64, 0.75ns, CMOS, LEAD FREE, DIMM-184; Categorystorage storage; File Size672KB，30 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT8VDDT6464AY-26AXX Overview

DDR DRAM Module, 64MX64, 0.75ns, CMOS, LEAD FREE, DIMM-184

MT8VDDT6464AY-26AXX Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Micron Technology
Parts packaging code	DIMM
package instruction	DIMM,
Contacts	184
Reach Compliance Code	compli
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.75 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N184
JESD-609 code	e4
memory density	4294967296 bi
Memory IC Type	DDR DRAM MODULE
memory width	64
Number of functions	1
Number of ports	1
Number of terminals	184
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX64
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Gold (Au)
Terminal form	NO LEAD
Terminal location	DUAL
Maximum time at peak reflow temperature	30

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128MB, 256MB, 512MB (x64, SR)

184-PIN DDR SDRAM UDIMM

DDR SDRAM

UNBUFFERED DIMM

Features

• 184-pin dual in-line memory module (DIMM)

• Fast data transfer rates: PC2100 or PC2700

• Utilizes 266 MT/s and 333 MT/s DDR SDRAM

components

• 128MB (16 Meg x 64), 256MB (32 Meg x 64), and

512MB (64 Meg x 64)

• V

= V

Q = +2.5V

• V

DDSPD

= +2.3V to +3.6V

• 2.5V I/O (SSTL_2 compatible)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Bidirectional data strobe (DQS) transmitted/

received with data—i.e., source-synchronous data

capture

• Differential clock inputs (CK and CK#)

• Four internal device banks for concurrent operation

• Programmable burst lengths: 2, 4, or 8

• Auto precharge option

• Auto Refresh and Self Refresh Modes

• 15.625µs (128MB), 7.8125µs (256MB, 512MB)

maximum average periodic refresh interval

• Serial Presence Detect (SPD) with EEPROM

• Programmable READ CAS latency

• Gold edge contacts

For the latest data sheet, please refer to the Micron



Web

site:

www.micron.com/products/modules

MT8VDDT1664A – 128MB

MT8VDDT3264A – 256MB

MT8VDDT6464A – 512MB

Figure 1: 184-Pin DIMM (MO-206)

Standard 1.25in. (31.75mm)

Low-Profile 1.15in. (29.21mm)

OPTIONS

MARKING

• Package

184-pin DIMM (standard)

184-pin DIMM (lead-free)

• Memory Clock/Speed, CAS Latency

6ns (167 MHz), 333 MT/s, CL = 2.5

-335

7.5ns (133 MHz), 266 MT/s, CL = 2

-262

7.5ns (133 MHz), 266 MT/s, CL = 2

-26A

7.5ns (133 MHz), 266 MT/s, CL = 2.5

-265

• PCB

Standard 1.25in. (31.75mm)

See page 2 note

Low-Profile 1.15in. (29.21mm)

See page 2 note

NOTE:

1. Consult Micron for product availability.

2. CL = CAS (READ) Latency

Table 1:

Address Table

128MB

256MB

8K (A0–A12)

4 (BA0, BA1)

256Mb (32 Meg x 8)

1K (A0–A9)

1 (S0#)

512MB

8K (A0–A12)

4 (BA0, BA1)

512Mb (64 Meg x 8)

2K (A0–A9, A11)

1 (S0#)

4K (A0–A11)

4 (BA0, BA1)

128Mb (16 Meg x 8)

1K (A0–A9)

1 (S0#)

Refresh Count

Row Addressing

Device Bank Addressing

Device Configuration

Column Addressing

Module Rank Addressing

pdf: 09005aef80867ab3, source: 09005aef80867a99

DD8C16_32_64x64AG.fm - Rev. G 9/04 EN

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

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