K3S7V2000M-TC30 datasheet, PDF

K3S7V2000M-TC

64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM

FEATURES

•

JEDEC standard 3.3V power supply

•

LVTTL compatible with multiplexed address

•

Address: Row address: RA

0

~ RA

12

Column address: CA

0

~ CA

7

(x32): CA

0

~ CA

8

(x16)

•

Switchable organization

4,194,304 x 16(word mode) /

2,097,152 x 32(double word mode)

•

All inputs are sampled at the rising edge of the system clock

•

Read Performance at memory point of view

@33MHz 4-1-1-1 (RAS Latency=1, CAS Latency=3)

@50MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4)

@66MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4)

@83MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5)

@100MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5)

•

t

SAC

: 6ns

•

Default mode by user requirement

•

MRS cycle with address key programs

-. RAS Latency(1 & 2)

-. CAS Latency(3 ~ 6)

-. Burst Length : 4, 8

-. Burst Type : Sequential & Interleaved

•

DQM for data-out masking

•

Package :86TSOP2 - 400

Synch. MROM

GENERAL DESCRIPTION

The K3S7V2000M-TC is a synchronous high bandwidth mask

programmable ROM fabricated with SAMSUNG′s high perfor-

mance CMOS process technology and is organized either as

4,194,304 x16bit(word mode) or as 2,097,152 x32bit(double

word mode) depending on polarity of WORD pin.(see pin func-

tion description). Synchronous design allows precise cycle con-

trol, with the use of system clock, I/O transactions are possible

on every clock cycle. Range of operating frequencies, program-

mable burst length and programmable latencies allow the same

device to be useful for a variety of high bandwidth, high perfor-

mance memory system applications.

ORDERING INFORMATION

Part NO.

K3S7V2000M-TC10

K3S7V2000M-TC12

K3S7V2000M-TC15

K3S7V2000M-TC20

K3S7V2000M-TC30

MAX Freq.

100MHz

83MHz

66MHz

50MHz

33MHz

LVTTL

86TSOP2

Interface

Package

FUNCTIONAL BLOCK DIAGRAM

Q0

Q16

.

Output

.

Buffer

Q15

Q31

Row Decoder

Sense AMP.

Row Buffer

4M x 16 /2M x 32

Cell Array

Address Register

CLK

ADD

Column Decoder

Col. Buffer

LRAS

Latency & Burst Length

LCKE

LRAS

LMR

LCAS

Timing

CLK

CKE

MR

Register

RAS

Programming Register

CAS

CS

DQM

*

Samsung Electronics reserves the right to

change products or specification without notice.

K3S7V2000M-TC

PIN CONFIGURATION (TOP VIEW)

Synch. MROM

V

DD

Q0

V

DD

Q

Q16

Q1

VssQ

Q17

Q2

V

DD

Q

Q18

Q3

VssQ

Q19

MR#

V

DD

DQM

NC

CAS#

RAS#

CS#

WORD#

A12

A11

A10

A0

A1

A2

NC

V

DD

NC

Q4

VssQ

Q20

Q5

V

DD

Q

Q21

Q6

VssQ

Q22

Q7

V

DD

Q

Q23

V

DD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

Vss

Q31

VssQ

Q15

Q30

V

DD

Q

Q14

Q29

VssQ

Q13

Q28

V

DD

Q

Q12

NC

Vss

NC

CLK

CKE

A9

A8

A7

A6

A5

A4

A3

NC

Vss

NC

Q27

V

DD

Q

Q11

Q26

VssQ

Q10

Q25

V

DD

Q

Q9

Q24

VssQ

Q8

Vss

86TSOPII - 400

(0.5 mm Pin Pitch)

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

K3S7V2000M-TC

PIN FUNCTION DESCRIPTION

CLK

CS

NAME

System Clock

Chip Select

INPUT FUNCTION

Active on the rising edge to sample all inputs.

Synch. MROM

Disables or enables device operation by masking or enabling all inputs except

CLK and CKE.

Masks system clock to freeze operation from the next clock cycle. CKE should be

enabled at least one cycle prior to new command. Disables input buffers for power down

in standby mode.

Row / Column addresses are multiplexed on the same pins.

Row address: RA

0

~ RA

12

, Column address: CA

0

~ CA

7

(x32): CA

0

~ CA

8

(x16)

Latches row addresses on the rising edge of the CLK with RAS low.

Enables row access

Latches column addresses on the rising edge of the CLK with CAS low.

Enables column access.

Enables mode register set with MR low. (Simultaneously CS,RAS and CAS are low)

CKE

Clock Enable

A

0

~ A

12

Address

RAS

CAS

MR

Q

0

~ Q

31

V

DD

/V

SS

V

DD

Q

/V

SS

Q

WORD

DQM

N.C

Row Address Strobe

Column Address Strobe

Mode Register Set

Data Output

Power Supply/Ground

Data Output Power/

Ground

x32/x16 Mode Selection

Data-out Masking

No Connection

Power and ground for the input buffers and the core logic.

Power and ground for the output buffers.

Double word mode/word mode, depending on polarity of WORD pin.

Should be set before CAS enabling.

It works similar to OE during read operation.

This pin is recommended to be left No Connection on the device.

Note1. V

DD

and V

DD

Q is same voltage.

K3S7V2000M-TC

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on V

DD

Relative to Vss

Voltage on Any Pin Relative to Vss

Operating Temperature

Storage Temperature

Short circuit current

Power Dissipation

Symbol

V

DD

, V

DD

Q

V

IN

, V

OUT

T

A

T

STG

I

OS

P

D

Min

-0.5

0

-55

-

Max

4.6

Synch. MROM

Unit

V

°C

mA

W

V

DD

+ 0.5≤4.6

70

125

50

1

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

DC OPERATING CONDITIONS

Recommended operating conditions(Voltage referenced to V

SS

, T

A

=0 to 70°C)

Parameter

Supply Voltage

Supply Voltage(Ground)

Symbol

V

DD

, V

DD

Q

V

SS,

V

SS

Q

Min

3.0

0

Typ

3.3

0

Max

3.6

0

Unit

V

DC CHARACTERISTICS

Parameter

Standby Current ( Note3)

Active Standby Current

Burst Mode Operating Current

Input Leakage Current

Output Leakage Current (Dout Disabled)

Input High Voltage, All Inputs

Input Low Voltage, All Inputs

Output High Voltage Level (Logic 1)

Output Low Voltage Level (Logic 0)

Symbol

I

CC3P

I

CC3PS

I

CC3N

I

CC4

I

IL

I

OL

V

IH

V

IL

V

OH

V

OL

Min

-

-10

2.0

-0.3

2.4

-

Max

150

50

100

10

V

DD

+ 0.3

0.8

-

0.4

Unit

uA

mA

uA

V

Test Condition

CKE≤V

IL

(Max), t

CC

=Min

CKE=0, t

CC

=Min

CS≥V

IH

(Min), t

CC

=Min,

All Outputs Open

t

CC

=Min, All Outputs Open

0V≤V

IN

≤V

DD

+ 0.3V

Pins not under test=0V

(0V≤V

OUT

≤V

DD

Max)

Q# in High-Z

(Note1)

(Note2)

I

OH

=-2mA

I

OL

=2mA

Note : 1. V

IH

(Max)=4.6V for pulse width≤10ns acceptable, pulse width measured at 50% of pulse amplitude.

2. V

IL

(Min)=-1.5V for pulse width≤10ns acceptable, pulse width measured at 50% of pulse amplitude.

3. The condition is the same as Self Refresh Mode of SDRAM, that is, in this case CS,RAS,CAS have to be set to Low, MR has to be set to High.

K3S7V2000M-TC

Parameter

Timing Reference Levels of Input/Output Signals

Input Signal Levels

Transition Time (Rise & Fall) of Input Signals

Output Load

Value

1.4V

Synch. MROM

AC OPERATING TEST CONDITIONS

(T

A

= 0 to 70°C, V

DD

= 3.3V±0.3V, unless otherwise noted.)

V

IH

/V

IL

=2.4V/0.4V

tr/tf=1ns/1ns

LVTTL

Note : If CLK transition time is longer than 1ns, timing parameters should be compensated. Add [(tr+tf)/2-1]ns for transition time longer than 1ns. Transi-

tion time is measured between V

IL

(Max) and V

IH

(Min).

3.3V

Vtt=1.4V

1200Ω

Output

870Ω

50pF

V

OH

(DC)=2.4V, I

OH

=-2mA

V

OL

(DC)=0.4V, I

OL

=2mA

Output

Z

0

=50Ω

50Ω

50pF

(Fig. 1) DC Output Load Circuit

(Fig. 2) AC Output Load Circuit

OPERATING AC PARAMETERS

(AC operating conditions unless otherwise noted)

Parameter

CLK Cycle Time

CLK to Valid Output Delay

Data Output Hold Time

CLK High Pulse Width

CLK Low Pulse Width

Row-active to Row-active

Input Setup Time

Input Hold Time

CLK to Output in Low-Z

CLK to Output in High-Z

Transition Time

Valid CAS Enable to Valid

CAS Enable

Symbol

t

CC

t

SAC

t

OH

t

CH

t

CL

t

RC

t

SS

t

SH

t

SLZ

t

SHZ

t

T

t

VCVC

up to 100MHz

Min

10

-

2

3

10

2

1

0

-

0.1

8

6

-

7

10

-

Max

up to 83MHz

Min

12

-

2

3.5

10

3

1

0

-

0.1

8

6

-

8

10

-

Max

up to 66MHz

Min

15

-

2

4

8

4

2

0

-

0.1

7

Max

-

6

-

10

-

up to 50 Mhz

Min

20

-

2

6.5

8

4

2

0

-

0.1

7

Max

-

6

-

15

10

-

ns

clks

ns

clks

2

1

Unit

Notes

Note :

1. These t

RC

values are for BL=8. For BL=4, t

RC

=6 clks for up to 100MHz, t

RC

=6 clks for up to 83MHz, t

RC

=4 clks for up to 66MHz, t

RC

=4 clks for up to

50MHz, and t

RC

=3 clks for up to 33MHz.

RAS latency increase means, a simultaneous t

RC

increase in the same number of cycles.

( If RAS latency is 3 clks, t

RC

is 12 clks for BL=8.) Refer to attached technical note for gapless operation.

2. These

t

VCVC

values are for BL=8. For BL=4,

t

VCVC

=4clks for up to 100MHz,

t

VCVC

=4clks for up to 83MHz,

t

VCVC

=3clks for up to 66MHz,

t

VCVC

=3clks for

up to 50MHz, and

t

VCVC

=2clks for up to 33MHz.

Refer to attached technical note for gapless operation.

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	TSOP2
package instruction	TSOP2, TSSOP86,.46,20
Contacts	86
Reach Compliance Code	compli
ECCN code	EAR99
Maximum access time	6 ns
Spare memory width	16
JESD-30 code	R-PDSO-G86
JESD-609 code	e0
length	22.22 mm
memory density	67108864 bi
Memory IC Type	MASK ROM
memory width	32
Number of functions	1
Number of terminals	86
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX32
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSSOP86,.46,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.00015 A
Maximum slew rate	0.1 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm

	K3S7V2000M-TC30	K3S7V2000M-TC	K3S7V2000M-TC12	K3S7V2000M-TC15
Description	64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM	64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM	64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM	64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM
Is it Rohs certified?	incompatible	-	incompatible	incompatible
Maker	SAMSUNG	-	SAMSUNG	SAMSUNG
Parts packaging code	TSOP2	-	TSOP2	TSOP2
package instruction	TSOP2, TSSOP86,.46,20	-	TSOP2, TSSOP86,.46,20	TSOP2, TSSOP86,.46,20
Contacts	86	-	86	86
Reach Compliance Code	compli	-	compli	compli
ECCN code	EAR99	-	EAR99	EAR99
Maximum access time	6 ns	-	6 ns	6 ns
Spare memory width	16	-	16	16
JESD-30 code	R-PDSO-G86	-	R-PDSO-G86	R-PDSO-G86
JESD-609 code	e0	-	e0	e0
length	22.22 mm	-	22.22 mm	22.22 mm
memory density	67108864 bi	-	67108864 bi	67108864 bi
Memory IC Type	MASK ROM	-	MASK ROM	MASK ROM
memory width	32	-	32	32
Number of functions	1	-	1	1
Number of terminals	86	-	86	86
word count	2097152 words	-	2097152 words	2097152 words
character code	2000000	-	2000000	2000000
Operating mode	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	-	70 °C	70 °C
organize	2MX32	-	2MX32	2MX32
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	-	TSOP2	TSOP2
Encapsulate equivalent code	TSSOP86,.46,20	-	TSSOP86,.46,20	TSSOP86,.46,20
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	-	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL	-	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
power supply	3.3 V	-	3.3 V	3.3 V
Certification status	Not Qualified	-	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	-	1.2 mm	1.2 mm
Maximum standby current	0.00015 A	-	0.00015 A	0.00015 A
Maximum slew rate	0.1 mA	-	0.1 mA	0.1 mA
Maximum supply voltage (Vsup)	3.6 V	-	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	-	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	-	3.3 V	3.3 V
surface mount	YES	-	YES	YES
technology	CMOS	-	CMOS	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	-	GULL WING	GULL WING
Terminal pitch	0.5 mm	-	0.5 mm	0.5 mm
Terminal location	DUAL	-	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
width	10.16 mm	-	10.16 mm	10.16 mm

K3S7V2000M-TC30

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