AGLN030Z2-QNG68I datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> AGLN030Z2-QNG68I

AGLN030Z2-QNG68I: DescriptionFPGA; CategoryProgrammable logic devices Programmable logic; File Size8MB，150 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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AGLN030Z2-QNG68I Overview

FPGA

AGLN030Z2-QNG68I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microsemi
package instruction	,
Reach Compliance Code	compli
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Maximum time at peak reflow temperature	NOT SPECIFIED

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Revision 16

IGLOO nano Low Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

nanoPower Consumption—Industry’s Lowest Power

1.2 V to 1.5 V Core Voltage Support for Low Power

Supports Single-Voltage System Operation

Low Power Active FPGA Operation

Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode

• As Small as 3x3 mm in Size

•

High-Performance Routing Hierarchy

Advanced I/Os

• Segmented, Hierarchical Routing and Clock Structure

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

• Selectable Schmitt Trigger Inputs

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO

Family

†

• Up to Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities, and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

• True Dual-Port SRAM (except × 18 organization)

†

• –20°C to +70°C

Small Footprint Packages

Wide Range of Features

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal, Flash-Based CMOS Process

Instant On Level 0 Support

Single-Chip Solution

Retains Programmed Design When Powered Off

250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

Performance

• 10,000 to 250,000 System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 71 User I/Os

Clock Conditioning Circuit (CCC) and PLL

In-System Programming (ISP) and Security

Embedded Memory

• ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)

• FlashLock

Designed to Secure FPGA Contents

• 1.2 V Programming

Enhanced Commercial Temperature Range

AGLN060

AGLN030Z

IGLOO nano Devices

IGLOO nano-Z Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM Kbits (1,024 bits)

4,608-Bit Blocks

Secure (AES)

AGLN010 AGLN015

AGLN020

10,000

260

–

2,3

AGLN125

AGLN250

AGLN060Z

60,000

512

1,536

Yes

CS81

VQ100

AGLN125Z

125,000

1,024

3,072

Yes

CS81

VQ100

AGLN250Z

250,000

2,048

6,144

Yes

CS81

VQ100

15,000

128

384

–

20,000

172

520

–

UC81,

CS81

QN68

30,000

256

768

–

UC81, CS81

QN48, QN68

VQ100

FlashROM Kbits (1,024 bits)

ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os (packaged device)

Maximum User I/Os (Known Good Die)

Package Pins

UC/CS

QFN

VQFP

–

UC36

QN48

QN68

Notes:

Not recommended for new designs.

AGLN030 and smaller devices do not support this feature.

AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs.

For higher densities and support of additional features, refer to the

IGLOO

and

IGLOOe

datasheets.

† AGLN030 and smaller devices do not support this feature.

December 2012

IGLOO nano Low Power Flash FPGAs

Table of Contents

IGLOO nano Device Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

IGLOO nano DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88

Pin Descriptions

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

3-2

3-3

3-4

3-5

Package Pin Assignments

UC36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

UC81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

CS81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

QN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

QN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

R ev i si o n 1 6

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