XPC857TZP80B datasheet, PDF - EEWORLD Datasheet

Advance Information

MPC862EC/D

Rev. 1.2, 8/2003

MPC862/857T/857DSL

Hardware Specifications

This document contains detailed information on power considerations, DC/AC electrical

characteristics, and AC timing speciﬁcations for the MPC862/857T/857DSL family (refer to

Table 1 for a list of devices). The MPC862P, which contains a PowerPC™ core processor, is

the superset device of the MPC862/857T/857DSL family.

This document describes pertinent electrical and physical characteristics of the MPC8245. For

functional characteristics of the processor, refer to the

MPC862 PowerQUICC Family Users

Manual

(MPC862UM/D).

This document contains the following topics:

Topic

Section 1, “Overview”

Section 2, “Features”

Section 3, “Maximum Tolerated Ratings”

Section 4, “Thermal Characteristics”

Section 5, “Power Dissipation”

Section 6, “DC Characteristics”

Section 7, “Thermal Calculation and Measurement”

Section 8, “Layout Practices”

Section 9, “Bus Signal Timing”

Section 10, “IEEE 1149.1 Electrical Speciﬁcations”

Section 11, “CPM Electrical Characteristics”

Section 12, “UTOPIA AC Electrical Speciﬁcations”

Section 13, “FEC Electrical Characteristics”

Section 14, “Mechanical Data and Ordering Information”

Section 15, “Document Revision History”

Page

1

2

7

9

10

11

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1

Overview

The MPC862/857T/857DSL is a derivative of Motorola’s MPC860 PowerQUICC™ family of

devices. It is a versatile single-chip integrated microprocessor and peripheral combination that

can be used in a variety of controller applications and communications and networking

systems. The MPC862/857T/857DSL provides enhanced ATM functionality over that of other

ATM-enabled members of the MPC860 family.

Features

Table 1 shows the functionality supported by the members of the MPC862/857T/857DSL family.

Table 1. MPC862 Family Functionality

Cache

Part

Instruction

Cache

16 Kbyte

4 Kbyte

Data Cache

8 Kbyte

4 Kbyte

Ethernet

SCC

10T

Up to 4

1

10/100

1

4

1

2

1

2

SMC

MPC862P

MPC862T

MPC857T

MPC857DSL

1

On the MPC857DSL, the SCC (SCC1) is for ethernet only. Also, the MPC857DSL does

not support the Time Slot Assigner (TSA).

2

On the MPC857DSL, the SMC (SMC1) is for UART only.

2

•

Features

Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with

thirty-two 32-bit general-purpose registers (GPRs)

— The core performs branch prediction with conditional prefetch, without conditional execution

— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).

– 16-Kbyte instruction cache (MPC862P) is four-way, set-associative with 256 sets; 4-Kbyte

instruction cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative

with 128 sets.

– 8-Kbyte data cache (MPC862P) is two-way, set-associative with 256 sets; 4-Kbyte data

cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative with 128 sets.

– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)

cache blocks.

– Caches are physically addressed, implement a least recently used (LRU) replacement

algorithm, and are lockable on a cache block basis.

— MMUs with 32-entry TLB, fully associative instruction and data TLBs

— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address

spaces and 16 protection groups

— Advanced on-chip-emulation debug mode

The MPC862/857T/857DSL provides enhanced ATM functionality over that of the MPC860SAR.

The MPC862/857T/857DSL adds major new features available in “enhanced SAR” (ESAR) mode,

including the following:

— Improved operation, administration and maintenance (OAM) support

— OAM performance monitoring (PM) support

— Multiple APC priority levels available to support a range of trafﬁc pace requirements

— ATM port-to-port switching capability without the need for RAM-based microcode

— Simultaneous MII (10/100Base-T) and UTOPIA (half-duplex) capability

The following list summarizes the key MPC862/857T/857DSL features:

•

2

MPC862/857T/857DSL Hardware Speciﬁcations

MOTOROLA

Features

•

— Optional statistical cell counters per PHY

— UTOPIA level 2 compliant interface with added FIFO buffering to reduce the total cell

transmission time. (The earlier UTOPIA level 1 speciﬁcation is also supported.)

— Multi-PHY support on the MPC857T

— Four PHY support on the MPC857DSL

— Parameter RAM for both SPI and I

2

C can be relocated without RAM-based microcode

— Supports full-duplex UTOPIA both master (ATM side) and slave (PHY side) operation using a

“split” bus

— AAL2/VBR functionality is ROM-resident

Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

32 address lines

Memory controller (eight banks)

— Contains complete dynamic RAM (DRAM) controller

— Each bank can be a chip select or RAS to support a DRAM bank

— Up to 30 wait states programmable per memory bank

— Glueless interface to Page mode/EDO/SDRAM, SRAM, EPROMs, ﬂash EPROMs, and other

memory devices.

— DRAM controller programmable to support most size and speed memory interfaces

— Four CAS lines, four WE lines, one OE line

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

— Variable block sizes (32 Kbyte–256 Mbyte)

— Selectable write protection

— On-chip bus arbitration logic

General-purpose timers

— Four 16-bit timers cascadable to be two 32-bit timers

— Gate mode can enable/disable counting

— Interrupt can be masked on reference match and event capture

Fast Ethernet controller (FEC)

— Simultaneous MII (10/100Base-T) and UTOPIA operation when using the UTOPIA

multiplexed bus.

System integration unit (SIU)

— Bus monitor

— Software watchdog

— Periodic interrupt timer (PIT)

— Low-power stop mode

— Clock synthesizer

— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture

— Reset controller

— IEEE 1149.1 test access port (JTAG)

Interrupts

— Seven external interrupt request (IRQ) lines

MOTOROLA

MPC862/857T/857DSL Hardware Speciﬁcations

3

Features

•

— 12 port pins with interrupt capability

— The MPC862P and MPC862T have 23 internal interrupt sources; the MPC857T and

MPC857DSL have 20 internal interrupt sources

— Programmable priority between SCCs (MPC862P and MPC862T)

— Programmable highest priority request

Communications processor module (CPM)

— RISC controller

— Communication-speciﬁc commands (for example,

GRACEFUL STOP TRANSMIT

,

ENTER HUNT

MODE

, and

RESTART TRANSMIT

)

— Supports continuous mode transmission and reception on all serial channels

— Up to 8-Kbytes of dual-port RAM

— The MPC862P and MPC862T have 16 serial DMA (SDMA) channels; the MPC857T and

MPC857DSL have 10 serial DMA (SDMA) channels

— Three parallel I/O registers with open-drain capability

Four baud rate generators

— Independent (can be connected to any SCC or SMC)

— Allow changes during operation

— Autobaud support option

The MPC862P and MPC862T have four SCCs (serial communication controller) The MPC857T

and MPC857DSL have one SCC, SCC1; the MPC857DSL supports ethernet only

— Serial ATM capability on all SCCs

— Optional UTOPIA port on SCC4

— Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation

— HDLC/SDLC

— HDLC bus (implements an HDLC-based local area network (LAN))

— Asynchronous HDLC to support PPP (point-to-point protocol)

— AppleTalk

— Universal asynchronous receiver transmitter (UART)

— Synchronous UART

— Serial infrared (IrDA)

— Binary synchronous communication (BISYNC)

— Totally transparent (bit streams)

— Totally transparent (frame based with optional cyclic redundancy check (CRC))

Two SMCs (serial management channels) (The MPC857DSL has one SMC, SMC1 for UART)

— UART

— Transparent

— General circuit interface (GCI) controller

— Can be connected to the time-division multiplexed (TDM) channels

One serial peripheral interface (SPI)

— Supports master and slave modes

— Supports multiple-master operation on the same bus

4

MPC862/857T/857DSL Hardware Speciﬁcations

MOTOROLA

Features

•

One inter-integrated circuit (I

2

C) port

— Supports master and slave modes

— Multiple-master environment support

Time-slot assigner (TSA) (The MPC857DSL does not have the TSA)

— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation

— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user deﬁned

— 1- or 8-bit resolution

— Allows independent transmit and receive routing, frame synchronization, clocking

— Allows dynamic changes

— On the MPC862P and MPC862T, can be internally connected to six serial channels (four SCCs

and two SMCs); on the MPC857T, can be connected to three serial channels (one SCC and two

SMCs)

Parallel interface port (PIP)

— Centronics interface support

— Supports fast connection between compatible ports on MPC862/857T/857DSL or MC68360

PCMCIA interface

— Master (socket) interface, release 2.1 compliant

— Supports one or two PCMCIA sockets dependent upon whether ESAR functionality is enabled

— 8 memory or I/O windows supported

Low power support

— Full on—All units fully powered

— Doze—Core functional units disabled except time base decrementer, PLL, memory controller,

RTC, and CPM in low-power standby

— Sleep—All units disabled except RTC, PIT, time base, and decrementer with PLL active for fast

wake up

— Deep sleep—All units disabled including PLL except RTC, PIT, time base, and decrementer.

— Power down mode— All units powered down except PLL, RTC, PIT, time base and

decrementer

Debug interface

— Eight comparators: four operate on instruction address, two operate on data address, and two

operate on data

— Supports conditions: =

≠

< >

— Each watchpoint can generate a break point internally

3.3 V operation with 5-V TTL compatibility except EXTAL and EXTCLK

357-pin plastic ball grid array (PBGA) package

Operation up to 100MHz

The MPC862/857T/857DSL is comprised of three modules that each use the 32-bit internal bus: the

MPC8xx core, the system integration unit (SIU), and the communication processor module (CPM). The

MPC862P/862T block diagram is shown in Figure 1. The MPC857T/857DSL block diagram is shown in

Figure 2.

MOTOROLA

MPC862/857T/857DSL Hardware Speciﬁcations

5

Parameter Name	Attribute value
Maker	Motorola ( NXP )
Parts packaging code	BGA
package instruction	BGA, BGA357,19X19,50
Contacts	357
Reach Compliance Code	unknow
ECCN code	3A001.A.3
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	80 MHz
External data bus width	32
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B357
length	25 mm
low power mode	YES
Number of terminals	357
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA357,19X19,50
Package shape	SQUARE
Package form	GRID ARRAY
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	2.05 mm
speed	80 MHz
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	25 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

	XPC857TZP80B	XPC862PZP50B	XPC857TZP100B	XPC857TCZP66B	XPC862PZP80B	XPC862TZP66B	XPC862PZP66B	XPC857DSLZP50B	XPC862TZP100B
Description	32-BIT, 80 MHz, RISC PROCESSOR, PBGA357, PLASTIC, BGA-357	32-BIT, 50MHz, RISC PROCESSOR, PBGA357, PLASTIC, BGA-357	32-BIT, 100MHz, RISC PROCESSOR, PBGA357, PLASTIC, BGA-357	32-BIT, 66MHz, RISC PROCESSOR, PBGA357, PLASTIC, BGA-357	32-BIT, 80MHz, RISC PROCESSOR, PBGA357, PLASTIC, BGA-357	32-BIT, 66MHz, RISC PROCESSOR, PBGA357, PLASTIC, BGA-357	32-BIT, 66 MHz, RISC PROCESSOR, PBGA357, PLASTIC, BGA-357	32-BIT, 50MHz, RISC PROCESSOR, PBGA357, PLASTIC, BGA-357	32-BIT, 100 MHz, RISC PROCESSOR, PBGA357, PLASTIC, BGA-357
Maker	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	BGA, BGA357,19X19,50	BGA,	BGA, BGA357,19X19,50	BGA, BGA357,19X19,50	BGA, BGA357,19X19,50	BGA, BGA357,19X19,50	BGA, BGA357,19X19,50	BGA,	BGA, BGA357,19X19,50
Contacts	357	357	357	357	357	357	357	357	357
Reach Compliance Code	unknow	unknown	unknown	unknown	unknown	unknown	unknow	unknow	unknow
ECCN code	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3
Address bus width	32	32	32	32	32	32	32	32	32
bit size	32	32	32	32	32	32	32	32	32
boundary scan	YES	YES	YES	YES	YES	YES	YES	YES	YES
maximum clock frequency	80 MHz	50 MHz	100 MHz	66 MHz	80 MHz	66 MHz	66 MHz	50 MHz	100 MHz
External data bus width	32	32	32	32	32	32	32	32	32
Format	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT
Integrated cache	YES	YES	YES	YES	YES	YES	YES	YES	YES
JESD-30 code	S-PBGA-B357	S-PBGA-B357	S-PBGA-B357	S-PBGA-B357	S-PBGA-B357	S-PBGA-B357	S-PBGA-B357	S-PBGA-B357	S-PBGA-B357
length	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm
low power mode	YES	YES	YES	YES	YES	YES	YES	YES	YES
Number of terminals	357	357	357	357	357	357	357	357	357
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.05 mm	2.05 mm	2.05 mm	2.05 mm	2.05 mm	2.05 mm	2.05 mm	2.05 mm	2.05 mm
speed	80 MHz	50 MHz	100 MHz	66 MHz	80 MHz	66 MHz	66 MHz	50 MHz	100 MHz
Maximum supply voltage	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC
Encapsulate equivalent code	BGA357,19X19,50	-	BGA357,19X19,50	BGA357,19X19,50	BGA357,19X19,50	BGA357,19X19,50	BGA357,19X19,50	-	BGA357,19X19,50
power supply	3.3 V	-	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	-	3.3 V

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