PCA9517
Level translating I
2
C-bus repeater
Rev. 03 — 30 January 2007
Product data sheet
1. General description
The PCA9517 is a CMOS integrated circuit that provides level shifting between low
voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I
2
C-bus or SMBus applications.
While retaining all the operating modes and features of the I
2
C-bus system during the
level shifts, it also permits extension of the I
2
C-bus by providing bidirectional buffering for
both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using
the PCA9517 enables the system designer to isolate two halves of a bus for both voltage
and capacitance. The SDA and SCL pins are over voltage tolerant and are
high-impedance when the PCA9517 is unpowered.
The 2.7 V to 5.5 V bus B-side drivers behave much like the drivers on the PCA9515A
device, while the adjustable voltage bus A-side drivers drive more current and eliminate
the static offset voltage. This results in a LOW on the B-side translating into a nearly 0 V
LOW on the A-side which accommodates smaller voltage swings of lower voltage logic.
The static offset design of the B-side PCA9517 I/O drivers prevent them from being
connected to another device that has rise time accelerator including the PCA9510,
PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517 (B-side),
or PCA9518. The A-side of two or more PCA9517s can be connected together, however,
to allow a star topography with the A-side on the common bus, and the A-side can be
connected directly to any other buffer with static or dynamic offset voltage. Multiple
PCA9517s can be connected in series, A-side to B-side, with no build-up in offset voltage
with only time of flight delays to consider.
The PCA9517 drivers are not enabled unless V
CCA
is above 0.8 V and V
CC
is above 2.5 V.
The EN pin can also be used to turn the drivers on and off under system control. Caution
should be observed to only change the state of the enable pin when the bus is idle.
The output pull-down on the B-side internal buffer LOW is set for approximately 0.5 V,
while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the
B-side I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a lock-up condition from occurring. The output pull-down on the A-side
drives a hard LOW and the input level is set at 0.3V
CCA
to accommodate the need for a
lower LOW level in systems where the low voltage side supply voltage is as low as 0.9 V.
2. Features
I
2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of
the device
I
Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V
I
Footprint and functional replacement for PCA9515/15A
I
I
2
C-bus and SMBus compatible
NXP Semiconductors
PCA9517
Level translating I
2
C-bus repeater
I
I
I
I
I
I
I
I
I
I
Active HIGH repeater enable input
Open-drain input/outputs
Lock-up free operation
Supports arbitration and clock stretching across the repeater
Accommodates Standard mode and Fast mode I
2
C-bus devices and multiple masters
Powered-off high-impedance I
2
C-bus pins
A-side operating supply voltage range of 0.9 V to 5.5 V
B-side operating supply voltage range of 2.7 V to 5.5 V
5 V tolerant I
2
C-bus and enable pins
0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be
less than 400 kHz because of the delays added by the repeater).
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Packages offered: SO8 and TSSOP8
3. Ordering information
Table 1.
Ordering information
T
amb
=
−
40
°
C to +85
°
C
Type number
PCA9517D
PCA9517DP
[1]
Topside
mark
Package
Name
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
SOT505-1
PCA9517 SO8
9517
TSSOP8
[1]
plastic thin shrink small outline package; 8 leads; body width 3 mm
Also known as MSOP8
4. Functional diagram
V
CCA
V
CCB
PCA9517
SDAA
SDAB
SCLA
V
CCB
pull-up
resistor
EN
002aac200
SCLB
GND
Fig 1. Functional diagram of PCA9517
PCA9517_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 30 January 2007
2 of 19
NXP Semiconductors
PCA9517
Level translating I
2
C-bus repeater
5. Pinning information
5.1 Pinning
V
CCA
SCLA
SDAA
GND
1
2
8
7
V
CCB
SCLB
SDAB
EN
V
CCA
SCLA
SDAA
GND
1
2
3
4
002aac199
8
7
V
CCB
SCLB
SDAB
EN
PCA9517D
3
4
002aac198
6
5
PCA9517DP
6
5
Fig 2. Pin configuration for SO8
Fig 3. Pin configuration for TSSOP8
(MSOP8)
5.2 Pin description
Table 2.
Symbol
V
CCA
SCLA
SDAA
GND
EN
SDAB
SCLB
V
CCB
Pin description
Pin
1
2
3
4
5
6
7
8
Description
A-side supply voltage (0.9 V to 5.5 V)
serial clock A-side bus
serial data A-side bus
supply ground (0 V)
active HIGH repeater enable input
serial data B-side bus
serial clock B-side bus
B-side supply voltage (2.7 V to 5.5 V)
6. Functional description
Refer to
Figure 1 “Functional diagram of PCA9517”.
The PCA9517 enables I
2
C-bus or SMBus translation down to V
CCA
as low as 0.9 V
without degradation of system performance. The PCA9517 contains two bidirectional
open-drain buffers specifically designed to support up-translation/down-translation
between the low voltage (as low as 0.9 V) and a 3.3 V or 5 V I
2
C-bus or SMBus. All inputs
and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered (V
CCB
and/or V
CCA
= 0 V). The PCA9517 includes a power-up circuit that keeps the output
drivers turned off until V
CCB
is above 2.5 V and the V
CCA
is above 0.8 V. V
CCB
and V
CCA
can be applied in any sequence at power-up. After power-up and with the enable (EN)
HIGH, a LOW level on the A-side (below 0.3V
CCA
) turns the corresponding B-side driver
(either SDA or SCL) on and drives the B-side down to about 0.5 V. When the A-side rises
above 0.3V
CCA
the B-side pull-down driver is turned off and the external pull-up resistor
pulls the pin HIGH. When the B-side falls first and goes below 0.3V
CCB
the A-side driver is
turned on and the A-side pulls down to 0 V. The B-side pull-down is not enabled unless
the B-side voltage goes below 0.4 V. If the B-side low voltage does not go below 0.5 V, the
A-side driver will turn off when the B-side voltage is above 0.7V
CCB
. If the B-side low
voltage goes below 0.4 V, the B-side pull-down driver is enabled and the B-side will only
PCA9517_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 30 January 2007
3 of 19
NXP Semiconductors
PCA9517
Level translating I
2
C-bus repeater
be able to rise to 0.5 V until the A-side rises above 0.3V
CCA
, then the B-side will continue
to rise being pulled up by the external pull-up resistor. The V
CCA
is only used to provide
the 0.3V
CCA
reference to the A-side input comparators and for the power good detect
circuit. The PCA9517 logic and all I/Os are powered by the V
CCB
pin.
6.1 Enable
The EN pin is active HIGH with an internal pull-up to V
CCB
and allows the user to select
when the repeater is active. This can be used to isolate a badly behaved slave on
power-up until after the system power-up reset. It should never change state during an
I
2
C-bus operation because disabling during a bus operation will hang the bus and
enabling part way through a bus cycle could confuse the I
2
C-bus parts being enabled.
The enable pin should only change state when the global bus and the repeater port are in
an idle state to prevent system failures.
6.2 I
2
C-bus systems
As with the standard I
2
C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I
2
C-bus).
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part designed to work with Standard mode and Fast
mode I
2
C-bus devices in addition to SMBus devices. Standard mode I
2
C-bus devices only
specify 3 mA output drive; this limits the termination current to 3 mA in a generic I
2
C-bus
system where Standard mode devices and multiple masters are possible. Under certain
conditions higher termination currents can be used.
Please see Application Note
AN255, I
2
C/SMBus Repeaters, Hubs and Expanders
for
additional information on sizing resistors and precautions when using more than one
PCA9517 in a system or using the PCA9517 in conjunction with other bus buffers.
PCA9517_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 30 January 2007
4 of 19
NXP Semiconductors
PCA9517
Level translating I
2
C-bus repeater
7. Application design-in information
A typical application is shown in
Figure 4.
In this example, the system master is running
on a 3.3 V I
2
C-bus while the slave is connected to a 1.2 V bus. Both buses run at 400 kHz.
Master devices can be placed on either bus.
3.3 V
1.2 V
10 kΩ
10 kΩ
10 kΩ
10 kΩ
V
CCB
SDA
SCL
BUS
MASTER
400 kHz
EN
bus B
SDAB
SCLB
V
CCA
SDAA
SCLA
SDA
SCL
PCA9517
SLAVE
400 kHz
bus A
002aac201
Fig 4. Typical application
The PCA9517 is 5 V tolerant, so it does not require any additional circuitry to translate
between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages.
When the A-side of the PCA9517 is pulled LOW by a driver on the I
2
C-bus, a comparator
detects the falling edge when it goes below 0.3V
CCA
and causes the internal driver on the
B-side to turn on, causing the B-side to pull down to about 0.5 V. When the B-side of the
PCA9517 falls, first a CMOS hysteresis type input detects the falling edge and causes the
internal driver on the A-side to turn on and pull the A-side pin down to ground. In order to
illustrate what would be seen in a typical application, refer to
Figure 8
and
Figure 9.
If the
bus master in
Figure 4
were to write to the slave through the PCA9517, waveforms shown
in
Figure 8
would be observed on the A bus. This looks like a normal I
2
C-bus transmission
except that the HIGH level may be as low as 0.9 V, and the turn on and turn off of the
acknowledge signals are slightly delayed.
On the B bus side of the PCA9517, the clock and data lines would have a positive offset
from ground equal to the V
OL
of the PCA9517. After the 8th clock pulse, the data line will
be pulled to the V
OL
of the slave device which is very close to ground in this example. At
the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9517 for a short delay while the A bus side rises above 0.3V
CCA
then it continues
HIGH. It is important to note that any arbitration or clock stretching events require that the
LOW level on the B bus side at the input of the PCA9517 (V
IL
) be at or below 0.4 V to be
recognized by the PCA9517 and then transmitted to the A bus side.
Multiple PCA9517 A-sides can be connected in a star configuration (Figure
5),
allowing all
nodes to communicate with each other.
Multiple PCA9517s can be connected in series (Figure
6)
as long as the A-side is
connected to the B-side. I
2
C-bus slave devices can be connected to any of the bus
segments. The number of devices that can be connected in series is limited by repeater
delay/time-of-flight considerations on the maximum bus speed requirements.
PCA9517_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 30 January 2007
5 of 19
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