MCM63P818ZP100R datasheet, PDF

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MCM63P818ZP100R: DescriptionIC,SYNC SRAM,256KX18,CMOS,BGA,119PIN,PLASTIC; Categorystorage storage; File Size452KB，21 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MCM63P818ZP100R Overview

IC,SYNC SRAM,256KX18,CMOS,BGA,119PIN,PLASTIC

MCM63P818ZP100R Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	unknow
ECCN code	3A991.B.2.A
Maximum access time	5 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B119
length	22 mm
memory density	4718592 bi
Memory IC Type	CACHE SRAM
memory width	18
Number of functions	1
Number of terminals	119
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX18
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	2.4 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	14 mm

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MOTOROLA

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM63P736/D

128K x 36 and 256K x 18 Bit

Pipelined BurstRAM

Synchronous Fast Static RAM

MCM63P736

MCM63P818

Freescale Semiconductor, Inc...

The MCM63P736 and MCM63P818 are 4M–bit synchronous fast static RAMs

designed to provide a burstable, high performance, secondary cache for the

PowerPC™ and other high performance microprocessors. The MCM63P736 is

organized as 128K words of 36 bits each, and the MCM63P818 is organized as

256K words of 18 bits each. These devices integrate input registers, an output

circuit for reduced parts count in cache data RAM applications. Synchronous

design allows precise cycle control with the use of an external clock (K).

Addresses (SA), data inputs (DQx), and all control signals except output

enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K) controlled

through positive–edge–triggered noninverting registers.

burst

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent

addresses can be generated internally by the MCM63P736

MCM63P818

and

(burst sequence operates in linear or interleaved mode dependent upon the state

input pin.

of LBO) and controlled by the burst address advance

(ADV) rising edge of the

Write cycles are internally self–timed and are initiated by the

write pulse generation

clock (K) input. This feature eliminates complex off–chip

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchro-

nous write enable (SW) are provided to allow writes to either individual bytes or

to all bytes. The bytes are designated as “a”, “b”, etc. SBa controls DQa, SBb

controls DQb, etc. Individual bytes are written if the selected byte writes SBx are

asserted with SW. All bytes are written if either SGW is asserted or if all SBx and

SW are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an

edge–triggered output register and then released to the output buffers at the next

rising edge of clock (K).

The MCM63P736 and MCM63P818 operate from a 3.3 V core power supply

and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs

are JEDEC standard JESD8–5 compatible.

•

MCM63P736/MCM63P818–133 = 4 ns Access/7.5 ns Cycle (133 MHz)

MCM63P736/MCM63P818–100 = 5 ns Access/10 ns Cycle (100 MHz)

MCM63P736/MCM63P818–66 = 7 ns Access/15 ns Cycle (66 MHz)

•

3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply

•

ADSP, ADSC, and ADV Burst Control Pins

•

Selectable Burst Sequencing Order (Linear/Interleaved)

•

Two–Cycle Deselect Timing

•

Internally Self–Timed Write Cycle

•

Byte Write and Global Write Control

•

Sleep Mode (ZZ)

•

JEDEC Standard 100–Pin TQFP and 119–Pin PBGA Packages

TQ PACKAGE

TQFP

CASE 983A–01

ZP PACKAGE

PBGA

CASE 999–02

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

REV 3

3/12/99

Motorola, Inc. 1999

MOTOROLA FAST SRAM

For More Information On This Product,

Go to: www.freescale.com

MCM63P736•MCM63P818

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