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NLX3G14EMUTCG

Description
3G SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8, 1.60 X 1 MM, 0.40 MM PITCH, LEAD FREE, UDFN-8
Categorylogic    logic   
File Size134KB,11 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance
Download Datasheet Parametric Compare View All

NLX3G14EMUTCG Overview

3G SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8, 1.60 X 1 MM, 0.40 MM PITCH, LEAD FREE, UDFN-8

NLX3G14EMUTCG Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerON Semiconductor
Parts packaging codeDFN
package instructionUDFN-8
Contacts8
Reach Compliance Codecompli
series3G
JESD-30 codeR-PDSO-N8
length1.6 mm
Load capacitance (CL)15 pF
Logic integrated circuit typeINVERTER
MaximumI(ol)0.008 A
Number of functions3
Number of entries1
Number of terminals8
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialPLASTIC/EPOXY
encapsulated codeVSON
Encapsulate equivalent codeSOLCC8,.04,16
Package shapeRECTANGULAR
Package formSMALL OUTLINE, VERY THIN PROFILE
method of packingTAPE AND REEL
power supply1.8/5 V
Prop。Delay @ Nom-Su9.1 ns
propagation delay (tpd)9.1 ns
Certification statusNot Qualified
Schmitt triggerYES
Maximum seat height0.55 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)1.65 V
Nominal supply voltage (Vsup)2.3 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formNO LEAD
Terminal pitch0.4 mm
Terminal locationDUAL
width1 mm
NLX3G14
Triple Schmitt-Trigger
Inverter
The NLX3G14 MiniGatet is an advanced high−speed CMOS
triple Schmitt−trigger inverter in ultra−small footprint.
The NLX3G14 input and output structures provide protection when
voltages up to 7.0 V are applied, regardless of the supply voltage.
The NLX3G14 can be used to enhance noise immunity or to square
up slowly changing waveforms.
Features
http://onsemi.com
MARKING
DIAGRAMS
ULLGA8
1.45 x 1.0
CASE 613AA
FM
Designed for 1.65 V to 5.5 V V
CC
Operation
Low Power Dissipation: I
CC
= 1
mA
(Max) at T
A
= 25°C
24 Balanced Output Source and Sink Capability
Balanced Propagation Delays
Overvoltage Tolerant (OVT) Input and Output Pins
Ultra−Small Packages
These are Pb−Free Devices
1
1
ULLGA8
1.6 x 1.0
CASE 613AB
ACM
G
1
IN A1
1
8
V
CC
ULLGA8
1.95 x 1.0
CASE 613AC
ACM
G
OUT Y3
2
7
OUT Y1
UDFN8
1.45 x 1.0
CASE 517BZ
XM
1
IN A2
3
6
IN A3
UDFN8
1.6 x 1.0
CASE 517BY
XM
1
GND
4
5
OUT Y2
UDFN8
1.95 x 1.0
CASE 517CA
XM
1
Figure 1. Pinout
(Top View)
1
1
1
IN A1
IN A2
IN A3
OUT Y1
OUT Y2
OUT Y3
F or AC = Specific Device Code
M
= Date Code
G
= Pb−Free Package
ORDERING INFORMATION
PIN ASSIGNMENT
1
2
3
4
IN A1
OUT Y3
IN A2
GND
OUT Y2
IN A3
OUT Y1
V
CC
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Figure 2. Logic Symbol
FUNCTION TABLE
A
L
H
Y
H
L
5
6
7
8
©
Semiconductor Components Industries, LLC, 2012
January, 2012
Rev. 1
1
Publication Order Number:
NLX3G14/D

NLX3G14EMUTCG Related Products

NLX3G14EMUTCG NLX3G14DMUTCG
Description 3G SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8, 1.60 X 1 MM, 0.40 MM PITCH, LEAD FREE, UDFN-8 3G SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8, 1.95 X 1 MM, 0.50 MM PITCH, LEAD FREE, UDFN-8
Is it Rohs certified? conform to conform to
Maker ON Semiconductor ON Semiconductor
Parts packaging code DFN DFN
package instruction UDFN-8 UDFN-8
Contacts 8 8
Reach Compliance Code compli compli
series 3G 3G
JESD-30 code R-PDSO-N8 R-PDSO-N8
length 1.6 mm 1.95 mm
Load capacitance (CL) 15 pF 15 pF
Logic integrated circuit type INVERTER INVERTER
MaximumI(ol) 0.008 A 0.008 A
Number of functions 3 3
Number of entries 1 1
Number of terminals 8 8
Maximum operating temperature 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code VSON VSON
Encapsulate equivalent code SOLCC8,.04,16 SOLCC8,.04,20
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE
method of packing TAPE AND REEL TAPE AND REEL
power supply 1.8/5 V 1.8/5 V
Prop。Delay @ Nom-Su 9.1 ns 9.1 ns
propagation delay (tpd) 9.1 ns 9.1 ns
Certification status Not Qualified Not Qualified
Schmitt trigger YES YES
Maximum seat height 0.55 mm 0.55 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V
Minimum supply voltage (Vsup) 1.65 V 1.65 V
Nominal supply voltage (Vsup) 2.3 V 2.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level MILITARY MILITARY
Terminal form NO LEAD NO LEAD
Terminal pitch 0.4 mm 0.5 mm
Terminal location DUAL DUAL
width 1 mm 1 mm
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