KM416RD8AC(D)/KM418RD8AC(D)
Revision History
Version 1.0 (July 1999) -
Preliminary
- Based on the Rambus Datasheet 1.0 ver.
Direct RDRAM
™
Version 1.01 (October 1999)
On page 1
- Delete the part numbers of low power.
On page 32
- Add the data of CNFGA Register @ Figure 28.
On page 33
- Add the data of CNFGB Register @ Figure 29 and correct the CORG4..0 field of CNFGB register.
On page 44
- Add the Tj value from TBD to Max. 100°C @ Table 18.
On page 46
- Add the
Θ
JC
value from TBD to 0.2°C/Watt @ Table 20.
On page 55
- Add the current values for 356MHz and 300MHz RDRAM device.
Page -1
Rev. 1.01 Oct. 1999
KM416RD8AC(D)/KM418RD8AC(D)
ORDERING INFORMATION
1
2
3
4
5
6
7
8
9
10
Direct RDRAM
™
KM 4 XX XX XX X X - X X XX
SAMSUNG Memory
Device
Organization
Product
Density
Speed
t
RAC
(Row Access Time)
Power & Refresh
Package Type
Revision
1. SAMSUNG Memory
7. Package Type
- C : u - BGA(Normal CSP)
- D : u - BGA(Mirrored CSP)
2. Device
- 4 : DRAM
3. Organization
- 16 : x16 bit
- 18 : x18 bit
8. Power & Refresh
- Blank : Normal Power Self Refesh(32m/8K, 3.9us)
-L
: Low Power Self Refesh(32m/8K, 3.9us)
-R
: Normal Power Self Refesh(32m/16K, 1.9us)
-S
: Low Power Self Refesh(32m/16K, 1.9us)
4. Product
- RD : Direct RAMBUS DRAM
5. Density
- 2 : 2M
- 4 : 4M
- 8 : 8M
- 16 : 16M
- 32 : 32M
6. Revision
- Blank : 1st Gen.
-A
: 2nd Gen.
9. t
RAC
(Row Access Time)
- Blank : for Daisy Chain Sample
-G
: 53.3ns
-K
: 45ns
-M
: 40ns
- B~D, F, J, L, N~ : Reserved
10. Speed
- DS : for Daisy Chain Sample
- 60 : 600Mbps (300MHz)
- 70 : 711Mbps (356MHz)
- 80 : 800Mbps (400MHz)
Page 0
Rev. 1.01 Oct. 1999
KM416RD8AC(D)/KM418RD8AC(D)
Overview
The Rambus Direct RDRAM™ is a general purpose high-
performance memory device suitable for use in a broad
range of applications including computer memory, graphics,
video, and any other application where high bandwidth and
low latency are required.
The 128/144-Mbit Direct Rambus DRAMs (RDRAM
®
) are
extremely high-speed CMOS DRAMs organized as 8M
words by 16 or 18 bits. The use of Rambus Signaling Level
(RSL) technology permits 600MHz to 800MHz transfer
rates while using conventional system and board design
technologies. Direct RDRAM devices are capable of
sustained data transfers at 1.25 ns per two bytes (10ns per
sixteen bytes).
The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's thirty-two
banks support up to four simultaneous transactions.
System oriented features for mobile, graphics and large
memory systems include power management, byte masking,
and x18 organization. The two data bits in the x18 organiza-
tion are general and can be used for additional storage and
bandwidth or for error correction.
Direct RDRAM
™
SEC KOREA
KM4xxRD8AC
SEC KOREA
KM4xxRD8AD
M
a. Normal Package
b. Mirrored Package
Figure 1: Direct RDRAM CSP Package
The 128/144-Mbit Direct RDRAMs are offered in a CSP
horizontal package suitable for desktop as well as low-
profile add-in card and mobile applications.
Key Timing Parameters/Part Numbers
Speed
Organization
Bin
256Kx16x32s
a
-RG60
-RK70
-RK80
256Kx18x32s
-RG60
-RK70
-RK80
I/O
Freq.
MHz
600
711
800
600
711
800
t
RAC
(Row
Access
Time) ns
53.3
45
45
53.3
45
45
Part Number
Features
♦
Highest sustained bandwidth per DRAM device
KM416RD8AC(D
b
)-R
c
G60
KM416RD8AC(D)-RK70
KM416RD8AC(D)-RK80
KM418RD8AC(D)-RG60
KM418RD8AC(D)-RK70
KM418RD8AC(D)-RK80
- 1.6GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simul-
taneously at full bandwidth data rates
♦
Low latency features
a.The
“32s"designation
indicates that this RDRAM core is composed of 32
banks which use a "split" bank architecture.
b.The
“C“
designator indicates the normal package and the
“D“
indicates the
mirrored package.
c.The
“R“
designator indicates that this RDRAM core uses Normal Power
Self Refresh.
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
♦
Advanced power management:
- Direct RDRAM operates from a 2.5 volt supply
- Multiple low power states allows flexibility in power
consumption versus time to transition to active state
- Power-down self-refresh
♦
Organization: 1Kbyte pages and 32 banks, x 16/18
- x18 organization allows ECC configurations or
increased storage/bandwidth
- x16 organization for low cost applications
♦
Uses Rambus Signaling Level (RSL) for up to 800MHz
operation
Page 1
Rev. 1.01 Oct. 1999
KM416RD8AC(D)/KM418RD8AC(D)
Pinouts and Definitions
Normal Package
This table shows the pin assignments of the normal RDRAM package.
Table 1 : a. Center-Bonded Device
(Top View For Normal Package)
12
11
10
9
8
7
6
5
4
3
2
1
ROW
COL
GND
VDD
VDD
GND
SCK
VCMOS
DQA8
*
DQA6
GND
DQA3
DQA1
VDD
DQA0
VREF
GND
CTMN
RQ7
GND
CTM
RQ1
VDD
RQ4
DQB2
GND
RQ0
DQB6
GND
DQB3
SIO0
VCMOS
DQB8
*
DQA7
GND
CMD
DQA4
VDD
DQA5
CFM
GND
DQA2
CFMN
GNDa
VDDa
RQ5
VDD
RQ6
RQ3
GND
RQ2
DQB0
VDD
DQB1
DQB4
VDD
DQB5
DQB7
GND
SIO1
GND
VDD
VDD
GND
Direct RDRAM
™
b.
Top marking
example of normal package
SEC KOREA
KM4xxRD8AC
For normal package, pin #1(ROW 1, COL A) is
located at the A1 position on the top side and
the A1 position is marked by the marker
“ “
.
Top View
A
B
C
D
E
F
G
H
J
Mirrored Package
This table shows the pin assignments of the mirrored RDRAM package.
Table 2: a.Center-Bonded Device
(Top View For Mirrored Package)
12
11
10
9
8
7
6
5
4
3
2
1
ROW
COL
GND
VDD
VDD
GND
CMD
GND
DQA7
DQA5
VDD
DQA4
DQA2
GND
CFM
VDDa
GNDa
CFMN
RQ6
VDD
RQ5
RQ2
GND
RQ3
DQB1
VDD
DQB0
DQB5
VDD
DQB4
SIO1
GND
DQB7
DQA8
*
VCMOS
SCK
DQA3
GND
DQA6
DQA0
VDD
DQA1
CTMN
GND
VREF
CTM
GND
RQ7
RQ4
VDD
RQ1
RQ0
GND
DQB2
DQB3
GND
DQB6
DQB8
*
VCMOS
SIO0
GND
VDD
VDD
GND
Chip
* DQA8/DQB8 are just used for
144Mb RDRAM. These two pins are
NC(No Connection) in 128Mb RDRAM.
b. Top marking example
of mirrored package
SEC KOREA
KM4xxRD8AD
M
A
B
C
D
E
F
G
H
J
For mirrored package, pin #1(ROW 1, COL A)
is located at the A1 postion on the top side and
the A1 position is marked by the alphabet
“
M
“
.
Page 2
Rev. 1.01 Oct. 1999
FPGA/CPLD
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