*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
Bi−Directional
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage (Note 2)
Reverse Leakage Current
Clamping Voltage (Note 3)
Clamping Voltage (Note 3)
ESD Clamping Voltage
Junction Capacitance
Dynamic Resistance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
V
C
C
J
R
DYN
I
T
= 1 mA
V
RWM
= 3.3 V
I
PP
= 1 A
I
PP
= 3 A
Per IEC61000−4−2
V
R
= 0 V, f = 1 MHz
V
R
= 0 V, f = 1 GHz
TLP Pulse
0.25
0.22
0.55
0.35
0.35
pF
W
5.0
6.0
< 1.0
Conditions
Min
Typ
Max
3.3
7.5
50
10
13
Unit
V
V
nA
V
V
2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.
3. Non−repetitive current pulse at T
A
= 25°C, per IEC61000−4−5 waveform.
www.onsemi.com
2
ESD7551, SZESD7551
1.E−03
1.E−04
CAPACITANCE (pF)
−6
−4
−2
0
V (V)
2
4
1.E−05
1.E−06
I (A)
1.E−07
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
6
8
0
−3
−2
−1
0
VBias (V)
1
2
3
1.E−08
1.E−09
1.E−10
1.E−11
1.E−12
−8
Figure 1. IV Characteristics
2
0
Db (ESD7551_882..S(2,1))
CAPACITANCE (pF)
−2
−4
−6
−8
−10
−12
−14
1.E+08
1.E+09
FREQUENCY (Hz)
1.E+10
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.0
2.0
Figure 2. CV Characteristics
3.0
4.0 5.0 6.0 7.0
FREQUENCY (GHz)
8.0
9.0
10
Figure 3. RF Insertion Loss
Figure 4. Capacitance over Frequency
16
14
TLP CURRENT (A)
12
10
8
6
4
2
0
0
2
4
6
8
12 14
10
VC, VOLTAGE (V)
16
18
8
−16
−14
EQUIVALENT V
IEC
(kV)
TLP CURRENT (A)
8
6
−12
−10
−8
−6
−4
−2
6
4
4
2
2
0
20
0
0
2
4
6
10
8
12 14
VC, VOLTAGE (V)
16
18
0
20
Figure 5. Positive TLP I−V Curve
Figure 6. Negative TLP I−V Curve
www.onsemi.com
3
EQUIVALENT V
IEC
(kV)
ESD7551, SZESD7551
IEC 61000−4−2 Spec.
Test Volt-
age (kV)
2
4
6
8
First Peak
Current
(A)
7.5
15
22.5
30
Current at
30 ns (A)
4
8
12
16
Current at
60 ns (A)
2
4
6
8
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
I @ 30 ns
IEC61000−4−2 Waveform
I
peak
100%
90%
Level
1
2
3
4
Figure 7. IEC61000−4−2 Spec
Device
ESD Gun
Under
Test
Oscilloscope
50
W
Cable
50
W
Figure 8. Diagram of ESD Test Setup
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
100
% OF PEAK PULSE CURRENT
90
80
70
60
50
40
30
20
10
0
0
20
t
P
t
r
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
PEAK VALUE I
RSM
@ 8
ms
PULSE WIDTH (t
P
) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8
ms
HALF VALUE I
RSM
/2 @ 20
ms
40
t, TIME (ms)
60
80
Figure 9. 8 x 20
ms
Pulse Waveform
www.onsemi.com
4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
X2DFNW2 1.0x0.6, 0.65P
CASE 711BG
ISSUE C
SCALE 8:1
DATE 13 SEP 2019
GENERIC
MARKING DIAGRAM*
XXM
XX = Specific Device Code
M = Date Code
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON15241G
X2DFNW2 1.0X0.6, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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