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24C01BJI-1.8TE13

Description
EEPROM, 128X8, Serial, CMOS, PDSO8, SOIC-8
Categorystorage    storage   
File Size64KB,7 Pages
ManufacturerCatalyst
Websitehttp://www.catalyst-semiconductor.com/
Download Datasheet Parametric View All

24C01BJI-1.8TE13 Overview

EEPROM, 128X8, Serial, CMOS, PDSO8, SOIC-8

24C01BJI-1.8TE13 Parametric

Parameter NameAttribute value
Parts packaging codeSOIC
package instructionSOP,
Contacts8
Reach Compliance Codeunknow
ECCN codeEAR99
Maximum clock frequency (fCLK)0.4 MHz
JESD-30 codeR-PDSO-G8
length4.9 mm
memory density1024 bi
Memory IC TypeEEPROM
memory width8
Number of functions1
Number of terminals8
word count128 words
character code128
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128X8
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialSERIAL
Certification statusNot Qualified
Maximum seat height1.75 mm
Serial bus typeI2C
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)1.8 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width3.9 mm
Maximum write cycle time (tWC)10 ms
Base Number Matches1
CAT24C01B
1K-Bit Serial EEPROM
FEATURES
I
2-Wire Serial Interface
I
1.8 to 6.0Volt Operation
I
Low Power CMOS Technology
I
4-Byte Page Write Buffer
I
Self-Timed Write Cycle with Auto-Clear
I
1,000,000 Program/Erase Cycles
I
100 Year Data Retention
I
8-pin DIP, 8-pin SOIC, 8-pin TSSOP or 8-pin MSOP
I
Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT24C01B is a 1K-bit Serial CMOS EEPROM
internally organized as 128 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces de-
vice power requirements. The CAT24C01B features a
4-byte page write buffer. The device operates via a 2-
wire serial interface and is available in 8-pin DIP, 8-pin
SOIC, 8-pin TSSOP or 8-pin MSOP.
PIN CONFIGURATION
DIP Package (P)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
BLOCK DIAGRAM
SOIC Package (J)
NC
NC
1
2
3
4
8
7
6
5
VCC
TEST
SCL
SDA
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SENSE AMPS
SHIFT REGISTERS
VCC
TEST
SCL
SDA
NC
VSS
5020 FHD F01
SDA
MSOP Package (R)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
TEST
SCL
SDA
NC
NC
NC
VSS
TSSOP Package (U)
1
2
3
4
8
7
6
5
VCC
TEST
SCL
SDA
START/STOP
LOGIC
XDEC
CONTROL
LOGIC
E
2
PROM
EEPROM
PIN FUNCTIONS
Pin Name
NC
SDA
SCL
V
CC
V
SS
TEST
Function
No Connect
Serial Data/Address
Serial Clock
+1.8V to +6.0V Power Supply
Ground
Test Input (GND, V
CC
or
Floating)
SCL
STATE COUNTERS
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
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