SM51208BSDT-7.5 datasheet, PDF

Datasheet> All Categories > storage> storage> SM51208BSDT-7.5

SM51208BSDT-7.5: DescriptionSynchronous DRAM Module, 64MX64, 5.4ns, CMOS, SODIMM-144; Categorystorage storage; File Size197KB，15 Pages; ManufacturerRamtron International Corporation (Cypress Semiconductor Corporation); Websitehttp://www.cypress.com/

Download Datasheet Parametric Compare View All

SM51208BSDT-7.5 Overview

Synchronous DRAM Module, 64MX64, 5.4ns, CMOS, SODIMM-144

SM51208BSDT-7.5 Parametric

Parameter Name	Attribute value
Maker	Ramtron International Corporation (Cypress Semiconductor Corporation)
Parts packaging code	MODULE
package instruction	,
Contacts	144
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N144
memory density	4294967296 bi
Memory IC Type	SYNCHRONOUS DRAM MODULE
memory width	64
Number of functions	1
Number of ports	1
Number of terminals	144
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX64
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal location	DUAL

SM51208BSDT-7.5 Preview

Preliminary Data Sheet

144-pin SDRAM SODIMMs

64MB, 128MB, 256MB, 512MB

Features

•

JEDEC Standard 144-pin PC133 SDRAM SODIMM

Fast 5.4 ns Clock Access Time

Supports CAS Latency = 2, 3

On-board Serial Presence Detect (SPD)

Unbuffered 144-pin SODIMM

4K Refresh / 64ms (8K Refresh for 512MB DIMM)

Single 3.3V

0.3V Power Supply

Symbol

Vss

DQ0

DQ32

DQ1

DQ33

DQ2

DQ34

DQ3

DQ35

Vdd

DQ4

DQ36

DQ5

DQ37

DQ6

DQ38

DQ7

DQ39

Vss

DQMB0

DQMB4

DQMB1

DQMB5

Vdd

Vss

Symbol

DQ8

DQ40

DQ9

DQ41

DQ10

DQ42

DQ11

DQ43

Vdd

DQ12

DQ44

DQ13

DQ45

DQ14

DQ46

DQ15

DQ47

Vss

RSVD

CK0

CKE0

Vdd

RAS#

CAS#

WE#

CKE1

S0#

A12

S1#

100

101

102

103

104

105

106

107

108

Symbol

RSVD

CK1

Vss

RSVD

Vdd

DQ16

DQ48

DQ17

DQ49

DQ18

DQ50

DQ19

DQ51

Vss

DQ20

DQ52

DQ21

DQ53

DQ22

DQ54

DQ23

DQ55

Vdd

BA0

Vss

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

Symbol

Vss

A10/AP

Vdd

DQMB2

DQMB6

DQMB3

DQMB7

Vss

DQ24

DQ56

DQ25

DQ57

DQ26

DQ58

DQ27

DQ59

Vdd

DQ28

DQ60

DQ29

DQ61

DQ30

DQ62

DQ31

DQ63

Vss

SDA

SCL

Vdd

Description

The Enhanced Memory Systems 64MB, 128MB, 256MB,

and 512MB Small Outline DIMMs (1.05-inch height) are the

fastest SODIMMs available for notebook and embedded

system applications. This PC133 product provides the lowest

cost for both PC133 and PC100 sockets. The fast 5.4 ns

clock access time allows unbuffered operation at 133 MHz

for lower memory latency, and lower costs than registered

DIMMs.

The 64MB module is organized as 8Mx64, the 128MB

module is organized as 16Mx64, the 256MB module is

organized as 32Mx64, and the 512MB module is organized

as 64Mx64. Each module has a serial presence EEPROM,

which contains information on the module type, module

organization, component speed, and other attributes relevant

to the system controller.

Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921

PHONE: (800) 545-DRAM; FAX: (719) 488-9095;

http://www.edram.com

The information contained herein is subject to change without notice.

Page 1 of 15

Revision 1.0

144-pin SDRAM SODIMMs

64MB, 128MB, 256MB, 512MB

Pin Descriptions

Symbol

CK(0:1)

CKE(0:1)

S(0:1)#

RAS#, CAS#,

WE#

BA(0:1)

A(0:12)

Preliminary Data Sheet

Type

Input

Function

Clocks: All SDRAM input signals are sampled on the positive edge of CK.

Clock Enables: CKE activate (high) or deactivate (low) the CK signals. Deactivating the clock initiates the

Power-Down and Self-Refresh operations (all banks idle), or Clock Suspend operation. CKE is synchronous until

the device enters Power-Down and Self-Refresh modes where it is asynchronous until the mode is exited.

Chip Select: S# enables (low) or disables (high) the command decoder. When the command decoder is

disabled, new commands are ignored but previous operations continue.

Command Inputs: Sampled on the rising edge of CK, these inputs define the command to be executed.

Bank Addresses: These inputs define to which of the 4 banks a given command is being applied.

Address Inputs: A0-A12 define the row address during the Bank Activate command. A0-A9 define the column

address during Read and Write commands. A10/AP invokes the Auto-precharge operation. During manual

Precharge commands, A10/AP low specifies a single bank precharge while A10/AP high precharges all banks.

The address inputs are also used to program the Mode Register.

Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these pins and must be set-up

and held relative to the rising edge of clock. For Read cycles, the device drives output data on these pins after

the CAS latency is satisfied.

Data I/O Mask Inputs: DQMB0-7 inputs mask write data (zero latency) and acts as a synchronous output enable

(2-cycle latency) for read data.

Power Supply: +3.3 V

Ground

Serial Presence-Detect Data: SDA is a bi-directional pin used to transfer addresses and data into

and data out of the presence-detect portion of the module.

DQ(0:63)

DQMB(0-7)

SDA

Input/

Output

Input

Supply

Input/

Output

Input

SCL

RFU

DNU

Serial Clock for Presence-Detect: SCL is used to synchronize the presence detect data transfer to

and from the module

Reserved for Future Use: These pins should be left unconnected.

Do not use.

No connect - open pin.

Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921

PHONE: (800) 545-DRAM; FAX: (719) 488-9095;

http://www.edram.com

Page 2 of 15

The information contained herein is subject to change without notice.

Revision 1.0

Preliminary Data Sheet

144-pin SDRAM SODIMMs

64MB, 128MB, 256MB, 512MB

64MB DIMM Functional Block Diagram – SM6408SDT

Clock Wiring

S0#

CK0

CK1

DQMB0

DQ(7:0)

DQMB4

DQ(39:32)

2 SDRAMs

CK0, CK1

2 SDRAMs

DQMB1

DQ(15:8)

DQMB5

DQ(47:40)

4 SDRAM

SCL

Serial PD

DQMB2

DQ(23:16)

DQ(55:48)

DQMB6

SDA

DQMB3

DQ(31:24)

DQMB7

DQ(63:56)

BA0

BA1

A0-A11

Vdd

Vss

BA0 SDRAM U0-7

BA1 SDRAM U0-7

A0-A11 SDRAM U0-7

Vdd SDRAM U0-7

Vss SDRAM U0-7

RAS#

CAS#

WE#

CKE0

RAS# SDRAM U0-7

CAS# SDRAM U0-7

WE# SDRAM U0-7

CKE SDRAM U0-7

Note:

All DQ resistor values are 10 ohms.

All CK resistor values are 10 ohms.

U0-U7 are 8Mx8 PC133 SDRAM devices.

Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921

PHONE: (800) 545-DRAM; FAX: (719) 488-9095;

http://www.edram.com

The information contained herein is subject to change without notice.

Page 3 of 15

Revision 1.0

144-pin SDRAM SODIMMs

64MB, 128MB, 256MB, 512MB

128MB DIMM Functional Block Diagram – SM12808ASDT

Preliminary Data Sheet

Clock Wiring

S0#

CK0

CK1

DQMB0

DQ(7:0)

DQMB4

DQ(39:32)

2 SDRAMs

CK0, CK1

2 SDRAMs

DQMB1

DQ(15:8)

DQMB5

DQ(47:40)

4 SDRAM

SCL

Serial PD

DQMB2

DQ(23:16)

DQ(55:48)

DQMB6

SDA

DQMB3

DQ(31:24)

DQMB7

DQ(63:56)

BA0

BA1

A0-A11

Vdd

Vss

BA0 SDRAM U0-7

BA1 SDRAM U0-7

A0-A11 SDRAM U0-7

Vdd SDRAM U0-7

Vss SDRAM U0-7

RAS#

CAS#

WE#

CKE0

RAS# SDRAM U0-7

CAS# SDRAM U0-7

WE# SDRAM U0-7

CKE SDRAM U0-7

Note:

All DQ resistor values are 10 ohms.

All CK resistor values are 10 ohms.

U0-U7 are 16Mx8 PC133 SDRAM devices.

Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921

PHONE: (800) 545-DRAM; FAX: (719) 488-9095;

http://www.edram.com

Page 4 of 15

The information contained herein is subject to change without notice.

Revision 1.0

Preliminary Data Sheet

144-pin SDRAM SODIMMs

64MB, 128MB, 256MB, 512MB

256MB DIMM Functional Block Diagram – SM25608ASDT

Clock Wiring

S0#

S1#

DQMB0

DQMB4

U0L

DQ(7:0)

U0U

DQ(39:32)

U4L

U4U

CK0

12pf

PLL

4 SDRAMs

DQMB1

CK1

DQMB5

U1L

DQ(15:8)

U1U

DQ(47:40)

SCL

Serial PD

DQMB2

U2L

DQ(23:16)

U2U

DQ(55:48)

BA0

BA1

DQMB3

U3L

DQ(31:24)

U3U

DQ(63:56)

Vdd

Vss

RAS#

CAS#

Note:

All DQ resistor values are 10 ohms.

All CK resistor values are 10 ohms.

U0-U7 are stacked 16Mx8 PC133 SDRAM devices.

WE#

CKE0

CKE1

Vdd SDRAM U0-7

Vss SDRAM U0-7

RAS# SDRAM U0-7

CAS# SDRAM U0-7

WE# SDRAM U0-7

CKE0 SDRAM U0-3

CKE0 SDRAM U4-7

DQMB7

U7L

U7U

A0-A11

A0-A11 SDRAM U0-7

BA0 SDRAM U0-7

BA1 SDRAM U0-7

DQMB6

U6L

U6U

CK0

CK1

PLL

Terminated

4 SDRAMs

U5L

U5U

12pf

SDA

Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921

PHONE: (800) 545-DRAM; FAX: (719) 488-9095;

http://www.edram.com

The information contained herein is subject to change without notice.

Page 5 of 15

Revision 1.0

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

SM51208BSDT-7.5 Related Products

	SM51208BSDT-7.5	SM25608ASDT-7.5	SM12808ASDT-7.5	SM6408SDT-7.5
Description	Synchronous DRAM Module, 64MX64, 5.4ns, CMOS, SODIMM-144	Synchronous DRAM Module, 32MX64, 5.4ns, CMOS, SODIMM-144	Synchronous DRAM Module, 16MX64, 5.4ns, CMOS, SODIMM-144	Synchronous DRAM Module, 8MX64, 5.4ns, CMOS, SODIMM-144
Maker	Ramtron International Corporation (Cypress Semiconductor Corporation)	Ramtron International Corporation (Cypress Semiconductor Corporation)	Ramtron International Corporation (Cypress Semiconductor Corporation)	Ramtron International Corporation (Cypress Semiconductor Corporation)
Parts packaging code	MODULE	MODULE	MODULE	MODULE
Contacts	144	144	144	144
Reach Compliance Code	unknow	unknown	unknown	unknow
ECCN code	EAR99	EAR99	EAR99	EAR99
access mode	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST
Maximum access time	5.4 ns	5.4 ns	5.4 ns	5.4 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N144	R-XDMA-N144	R-XDMA-N144	R-XDMA-N144
memory density	4294967296 bi	2147483648 bit	1073741824 bit	536870912 bi
Memory IC Type	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE
memory width	64	64	64	64
Number of functions	1	1	1	1
Number of ports	1	1	1	1
Number of terminals	144	144	144	144
word count	67108864 words	33554432 words	16777216 words	8388608 words
character code	64000000	32000000	16000000	8000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	64MX64	32MX64	16MX64	8MX64
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
self refresh	YES	YES	YES	YES
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal location	DUAL	DUAL	DUAL	DUAL

Recommended Resources

Photodiode optical signal amplification and switching circuit

Fully automatic monitoring circuit diagram of generator starting battery

Two-dimensional pattern lantern controller circuit 02

Touch alarm electronic door lock circuit

High efficiency battery charger circuit

BG602 integrated voltage regulator using composite transistor for current expansion

Request for xilinx ise 12.4 crack version download: :)Thank you so much...; zzy时间 FPGA/CPLD

I am a novice learning Bluetooth. Can someone please guide me on which chip is more suitable for learning and development?: Due to the company's requirements, I was transferred to work on Bluetooth, mainly audio. The company's requirement is that when the Bluetooth function is turned on, Bluetooth collects sound signals in...; wuyusheng318 RF/Wirelessly

Help: Serial port data feedback in HyperTerminal: I send characters from the PC keyboard to the board's COM0, and then transmit the characters received by COM0 back to the HyperTerminal for display. But now the HyperTerminal does not display the inpu...; neaman stm32/stm8

An error in the MSP430G2553 data sheet regarding the ADC10 output reference voltage: When learning about MSP430G2553, I read the data sheet and learned that the internal reference voltage can be output from VREF+ using pin P1.4. However, I found two contradictory statements in the Dat...; sywcxx Microcontroller MCU

UC/OS ii problem with stm32, please advise: I found an STM32 board to run UC/OSII, and used IAR5.2 as the environment. When emulating, it jumped to address 80024F4, but the FLASH is set to start from 800,000 and there are not only vector tables...; jhxia0156 stm32/stm8

Recruiting partners for drone high-speed communication project: [font=Verdana, Helvetica, Arial, sans-serif]UAV high-speed communication project: Building a broadband wireless communication system for drones. [/font][font=Verdana, Helvetica, Arial, sans-serif]Loca...; wlcsys FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components