Features
•
One-Time Programmable (OTP) Feature
•
Low-Voltage and Standard-Voltage Operation
– 5.0 (V
CC
= 4.5V to 5.5V)
– 2.7 (V
CC
= 2.7V to 5.5V)
– 1.8 (V
CC
= 1.8V to 3.6V)
Internally Organized 16,384 x 8 and 32,768 x 8
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
64-Byte Page Write Mode (Partial Page Writes Allowed)
Self-Timed Write Cycle (5 ms typical)
High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
– ESD Protection: >4000V
Automotive Grade and Extended Temperature Devices Available
8-Pin JEDEC PDIP and 8-Pin JEDEC and EIAJ SOIC Packages
•
•
•
•
•
•
•
•
•
•
•
2-Wire Serial
EEPROMs
with Permanent
Software Write
Protect
128K (16,384 x 8)
256K (32,768 x 8)
Description
The AT24CS128/256 provides 131,072/262,144 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8
bits each. The device’s cascadable feature allows up to 4 devices to share a common
2-wire bus. The device also features a one-time programmable 2048 bit array, which
once enabled, becomes read-only and cannot be overwritten. If not enabled, the OTP
section will function as part of the normal memory array. The device is optimized for
use in many industrial and commercial applications where low power and low voltage
operation are essential. The devices are available in space-saving 8-pin JEDEC PDIP
(AT24CS128/256), 8-pin EIAJ (AT24CS128/256), 8-pin JEDEC SOIC (AT24CS128)
packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V
to 5.5V) and 1.8V (1.8V to 3.6V) versions.
Pin Configurations
Pin Name
A0 to A2
SDA
SCL
WP
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
A0
A1
A2
GND
8-Pin PDIP
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
AT24CS128
AT24CS256
with Permanent
Software Write
Protect
Advanced
Information
8-Pin SOIC
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
Rev. 1152A–09/98
1
Absolute Maximum Ratings*
Operating Temperature .................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage........................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Block Diagram
A
2
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bidirectional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0):
The A1 and
A0 pins are device address inputs that are hardwired or left
not connected for hardware compatibility with AT24C32/64.
When the pins are hardwired, as many as four 128K/256K
devices may be addressed on a single bus system (device
addressing is discussed in detail under the Device
Addressing section). When the pins are not hardwired, the
default A
1
and A
0
are zero. The A2 device address input is
a “don’t care” input.
WRITE PROTECT (WP):
The write protect input, when tied
to GND, allows normal write operations. When WP is tied
high to V
CC
, all write operations to the memory are inhib-
ited. If left unconnected, WP is internally pulled down to
GND. Switching WP to V
CC
prior to a write operation cre-
ates a software write protect function.
Memory Organization
AT24CS128/256, 128K/256K SERIAL EEPROM:
The
128K/256K is internally organized as 256/512 pages of 64-
bytes each. Random word addressing requires a 14/15-bit
data word address.
2
AT24CS128/256
AT24CS128/256
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +1.8V.
Symbol
C
I/O
C
IN
Note:
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A
0
, A
1
, SCL)
This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AI
= -40°C to +85°C, V
CC
= +1.8V to +5.5V, T
AC
= 0°C to +70°C,
V
CC
= +1.8V to +5.5V (unless otherwise noted).
Symbol
V
CC1
V
CC2
V
CC3
I
CC1
I
CC2
I
SB1
Parameter
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
Supply Current
Standby Current
(1.8V option)
Standby Current
(2.7V option)
Standby Current
(5.0V option)
Input Leakage Current
Output Leakage Current
Input Low Level
(Note:)
Input High Level
(Note:)
Output Low Level
Output Low Level
V
CC
= 3.0V
V
CC
= 1.8V
I
OL
= 2.1 mA
I
OL
= 0.15 mA
V
CC
= 5.0V
V
CC
= 5.0V
V
CC
= 1.8V
V
CC
= 3.6V
V
CC
= 2.7V
V
CC
= 5.5V
V
CC
= 4.5 - 5.5V
READ at 400 kHz
WRITE at 400 kHz
V
IN
= V
CC
or V
SS
Test Condition
Min
1.8
2.7
4.5
1.0
2.0
Typ
Max
3.6
5.5
5.5
2.0
3.0
0.2
2.0
0.5
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
OUT
= V
CC
or V
SS
-0.6
V
CC
x 0.7
0.10
0.05
5.0
5.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
µA
µA
µA
V
V
V
V
µA
Units
V
V
V
mA
mA
µA
I
SB2
I
SB3
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note:
V
IL
min and V
IH
max are reference only and are not tested
3
AC Characteristics
Applicable over recommended operating range from T
A
= -40°C to +85°C, V
CC
= +1.8V to +5.5V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
1.8-volt
Symbol
f
SCL
t
LOW
t
HIGH
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
(1)
Notes:
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Time the bus must be free before a new
transmission can start
(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time
(1)
Inputs Fall Time
(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Page Mode
100K
0.6
50
20
100K
1.3
1.0
0.1
1.2
0.6
0.6
0
100
0.3
300
0.25
50
10
100K
0.9
Min
Max
400
0.6
0.4
0.05
0.5
0.25
0.25
0
100
0.3
100
0.25
50
10
0.55
2.7-volt
Min
Max
1000
0.6
0.4
0.05
0.5
0.25
0.25
0
100
0.3
100
0.55
5.0-volt
Min
Max
1000
Units
kHz
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write
Cycles
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
R
L
(connects to V
CC
): 1.3KΩ (2.7V, 5V), 10KΩ (1.8V)
Input pulse voltages: 0.3V
CC
to 0.7V
CC
Input rise and fall times:
≤50ns
Input and output timing reference voltages: 0.5V
CC
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as defined
below.
START CONDITION:
A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
STOP CONDITION:
A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE:
All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE:
The AT24CS128/256 features a low
power standby mode which is enabled: a) upon power-up
and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET:
After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps: (a) Clock up to 9 cycles, (b) look for SDA
high in each cycle while SCL is high and then (c) create a
start condition as SDA is high.
4
AT24CS128/256
AT24CS128/256
Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
SCL
SDA
8th BIT
WORD n
ACK
t
WR
STOP
CONDITION
(1)
START
CONDITION
Note:
1.
The write cycle time t
WR
is the time from a valid stop condition of a write sequence to the end of the internal clear/write
cycle.
5
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