DATASHEET
ZL2102
6A Digital Integrated Synchronous Step-Down DC/DC Regulator with Auto
Compensation
The ZL2102 is an integrated digital power regulator with auto
compensation and power management functions in a small
package, resulting in a flexible and integrated solution, which
can be configured using the PowerNavigator™ graphical user
interface. This synchronous buck converter operates from a
4.5V to 14V input supply and provides from 0.54V to 5.5V
output voltage at up to 6A.
The ZL2102 can be configured for most applications using only
hardware pin straps to adjust switching frequency, output
voltage, UVLO, soft-start ramp/delay settings, sequencing
options, and SMBus address. For more advanced
configurations, the ZL2102 supports over 70 PMBus
commands. Output voltage/current is factory calibrated.
Internal synchronous power MOSFETs enable the ZL2102 to
deliver continuous loads up to 6A with high efficiency. An
internal Schottky bootstrap diode reduces discrete component
count. The ZL2102 also supports phase spreading to reduce
system input capacitance.
The ZL2102 uses the SMBus™ with PMBus™ protocol for
communication with a host controller and the Intersil's
proprietary Digital-DC™ bus for interoperability between other
Intersil devices.
FN8440
Rev 2.00
November 20, 2014
Features
• Integrated MOSFET switches
• 6A continuous output current
• Adjustable 0.54V to 5.5V output range
• 4.5V to 14V input range
• Up to 90% efficiency
• Auto compensation for fast transient response
• SMBus compliant serial interface
• Snapshot™ parametric capture
• Internal nonvolatile memory
• Small footprint QFN package (6mmx6mm)
Applications
• Servers/storage equipment
• Telecom/datacom equipment
• Power supplies (memory, DSP, ASIC, FPGA)
Related Literature
•
AN2010
"Thermal and Layout Guidelines for Digital-DC™
Products"
•
AN2035
"Compensation Using CompZL™"
•
TB389
"PCB Land Pattern and Surface Mount Guidelines for
QFN Packages"
DDC Bus
INTERFACE
SMBus
DDC
SCL
SDA
SALRT
PG
V2P5
VRA
10µF
4.7µF
4.7µF
ZL2102
VR
VDDS
VDDP
C
B
0.1µF
BST
V
IN
12V
C
IN
100µF
L
OUT
2.2µH
V
OUT
3.3V
6A
C
OUT
200µF
HARDWARE
CONTROL
MGN
EN
SYNC
VSET
HARDWARE
CONFIG
SA
FC
CFG
SS
SW
VSEN
PGND
SGND
DGND
ePAD
FIGURE 1. TYPICAL APPLICATION DIAGRAM
FN8440 Rev 2.00
November 20, 2014
Page 1 of 58
ZL2102
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Digital-DC Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Conversion Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SMBus Device Address Selection (SA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Voltage and VOUT_MAX Selection (VSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Automatic Loop Compensation (FC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Synchronization and Sequencing Configuration Settings (CFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Switching Frequency Setting (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Soft-Start and UVLO Settings (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Start-up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Management Function Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitoring via SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nonvolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Snapshot™ Parametric Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Train Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Goal Trade-offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
14
14
15
15
15
15
15
16
16
16
16
16
17
17
17
17
18
PCB Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PMBus Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PMBus Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PMBus Command Detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
FN8440 Rev 2.00
November 20, 2014
Page 2 of 58
ZL2102
FIGURE 2. BLOCK DIAGRAM
Pin Configuration
ZL2102
(36 LD 6x6 QFN)
TOP VIEW
30 VDDS
29 VDDP
28 VDDP
27 VDDP
26 BST
25 SW
24 SW
23 SW
22 SW
21 SW
20 SW
19 PGND
CFG 10
SS 11
DNC 12
VSEN 13
SGND 14
PGND 15
PGND 16
PGND 17
PGND 18
33 V2P5
35 MGN
34 DDC
32 VRA
36 EN
31 VR
PG 1
DGND 2
SYNC 3
VSET 4
SA 5
SCL 6
SDA 7
SALRT 8
FC 9
EXPOSED PADDLE
CONNECT TO SGND
FN8440 Rev 2.00
November 20, 2014
Page 3 of 58
ZL2102
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15, 16,
17, 18, 19
20, 21,
22, 23,
24, 25
26
27, 28, 29
30
31
32
33
34
35
36
ePad
PIN NAME
PG
DGND
SYNC
VSET
SA
SCL
SDA
SALRT
FC
CFG
SS
DNC
VSEN
SGND
PGND
SW
TYPE
Output
Ground
DESCRIPTION
Power-good indicator output pin. This pin transitions high after the output voltage stabilizes within the regulation
band. Selectable open-drain or push-pull output. Default is open drain.
Digital ground. This is the common return for digital signals. Connect to low impedance ground plane.
Multimode Clock synchronization I/O pin. Used to set switching frequency of internal clock or for synchronization to an external
clock, depending on the setting of the CFG pin. Configured during start-up by pin strap.
Multimode Output voltage select pin. Used to set V
OUT
set-point and V
OUT
max. Configured during start-up by pin strap.
Multimode Serial address select pin. Used to assign a unique SMBus address to the device. Configured during start-up by pin strap.
I/O
I/O
Output
Serial clock pin for SMBus communication. Connect to external host interface. A pull-up resistor is required for
operation.
Serial data pin for SMBus communication. Connect to external host interface. A pull-up resistor is required for
operation.
Serial alert output pin for SMBus communication. Connect to external host interface if desired.
Multimode Auto compensation configuration pin. Used to set up auto compensation configuration. Configured during start-up
by pin strap.
Multimode Configuration pin. Used to configure the SYNC pin and sequencing options. Configured during start-up by pin strap.
Multimode Soft-start pin. Sets the ramp delay/ramp time and UVLO. Configured during start-up by pin strap.
No Connect Do not connect to pin. Leave floating.
Input
Ground
Ground
Output
Output voltage positive feedback sense pin.
Common return for analog signals. Connect to low impedance ground plane at one point directly at PGND pins.
Power ground. Common return for internal switching MOSFETs and external C
IN
/C
OUT
. Connect to low impedance
ground plane.
Output switch node to the inductor.
BST
VDDP
VDDS
VR
VRA
V2P5
DDC
MGN
EN
SGND
Input
Power
Power
Power
Power
Power
I/O
Input
Input
Ground
Boosted floating driver supply pin. The bootstrap capacitor connects from the switch node to this pin.
Supply voltage for internal switching MOSFETs.
Supply voltage for the IC.
Regulated bias from internal 7V low-dropout regulator. Decouple with a 4.7μF capacitor to GND. Not for use with
external circuits.
Regulated bias from internal 5V low-dropout regulator for internal analog circuitry. Decouple with a 4.7μF capacitor
to GND. Not for use with external circuits.
Regulated bias from internal 2.5V low-dropout regulator for internal digital circuitry. Decouple with a 10µF capacitor
to GND. Connect the device's multimode pins to this supply pin for logic HIGH pin strap settings.
Digital-DC Bus pin. Allows interoperability between other Intersil devices. A pull-up resistor is required for operation.
Margin setting pin, used to enable margining of the output voltage. Logic HIGH sets the device to margin high, logic
LOW sets the device to margin low, and leaving the pin floating sets the device to nominal voltage output.
Enable pin, used to enable the output. Default is active high.
Exposed thermal pad. Common return for analog signals. Connect to low impedance ground plane.
Ordering Information
PART NUMBER
(Notes
1, 2, 3
ZL2102ALAFTK
NOTES:
1. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ZL2102.
For more information on MSL, please see tech brief
TB363.
PART MARKING
2102
TEMP RANGE
(°C)
-40 to +85
PACKAGE
Tape & Reel (Pb-free)
36 Ld Exposed Pad 6x6 QFN
PKG.
DWG. #
L36.6x6A
FN8440 Rev 2.00
November 20, 2014
Page 4 of 58
ZL2102
Absolute Maximum Ratings
DC Supply Voltage for VDDP, VDDS Pins . . . . . . . . . . . . . . . . . . -0.3V to 17V
High-Side Supply Voltage for BST Pin. . . . . . . . . . . . . . . . . . . . -0.3V to 25V
High-Side Boost Voltage for BST, SW Pins. . . . . . . . . . . . . . . . . . -0.3V to 8V
Internal MOSFET Reference for VR Pin . . . . . . . . . . . . . . . . . . -0.3V to 8.5V
Internal Analog Reference for VRA Pin . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Internal 2.5V Reference for V2P5 Pin . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V
Logic I/O Voltage for EN, CFG, DDC, FC, MGN, PG, SDA, SCL,
SA, SALRT, SS, SYNC, VSET, VSEN Pins . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Ground Differential for DGND - SGND, PGND - SGND Pins . . . . . . . . ±0.3V
MOSFET Drive Reference Current for VR Pin Internal Bias Usage . . . 20mA
Switch Node Current for SW Pin Peak (Sink Or Source) . . . . . . . . . . . . 10A
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V
Latch-up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
36 Ld QFN Package (Notes
4, 5)
. . . . . . . .
28
1.7
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Dissipation Limits (Note
6)
T
A
= +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5W
T
A
= +55°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5W
T
A
= +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4W
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
Recommended Operating Conditions
Input Supply Voltage Range, VDDP, VDDS (see
Figure 10 on page 10)
VDDS tied to VR, VRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
VDDS tied to VR, VRA Floating . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V to 7.5V
VR, VRA Floating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.5V to 14V
Output Voltage Range, V
OUT
(Note
7)
. . . . . . . . . . . . . . . . . . . 0.54V to 5.5V
Operating Junction Temperature Range, T
J
. . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured in free air with the device mounted on a multi-layer FR4 test board and the exposed metal pad soldered to a low impedance ground
plane using multiple vias.
5. For
JC
, the "case temp" location is the center of the exposed metal pad on the package underside.
6. Thermal impedance is dependent upon PCB layout.
7. Includes margin limits.
Electrical Specifications
VDDP = VDDS = 12V, T
A
= -40°C to +85°C unless otherwise noted (Note
9).
Typical values are at
T
A
= +25°C.
Boldface limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
MIN
(Note
8)
TYP
MAX
(Note
8)
UNIT
IC INPUT AND BIAS SUPPLY CHARACTERISTICS
I
DD
Supply Current
f
SW
= 200kHz, no load
f
SW
= 1MHz, no load
I
DD
Shutdown Current
VR Reference Output Voltage
VRA Reference Output Voltage
V2P5 Reference Output Voltage
EN = 0 V, no SMBus activity, low power standby
mode
V
DD
> 8V, IVR < 10mA
V
DD
> 5.5V, IVRA < 20mA
IV2P5 < 20mA
–
–
–
6.5
4.5
2.25
15
15
0.6
7.0
5.1
2.5
25
30
1
7.5
5.5
2.75
mA
mA
mA
V
V
V
OUTPUT CHARACTERISTICS
Output Current
I
RMS
, continuous
Peak (Note
11)
Output Voltage Adjustment Range (Note
10)
Output Voltage Set-point Accuracy
Output Voltage Set-point Resolution
VSEN Input Bias Current
V
IN
> V
OUT
Across line, load, temperature variation
Set using PMBus command
V
SEN
= 5.5V
–
–
0.6
-1
–
–
–
–
–
–
±2
110
6
9
5.0
1
–
200
A
A
V
%
mV
µA
FN8440 Rev 2.00
November 20, 2014
Page 5 of 58
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