K4S283232E-T
1M x 32Bit x 4 Banks SDRAM in 86TSOP2
FEATURES
•. 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
•. Burst read single-bit write operation
• DQM for masking
•. Auto & self refresh
•. 64ms refresh period (4K cycle).
•. 86TSOP2.
CMOS SDRAM
GENERAL DESCRIPTION
The K4S283232E is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
ORDERING INFORMATION
Part No.
K4S283232E-TC/L60
K4S283232E-TC/L75
K4S283232E-TC/L1L
Max Freq. Interface Package
166MHz(CL=3)
133MHz(CL=3) LVTTL 86TSOP2
100MHz(CL=3)
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
LDQM
Data Input Register
Bank Select
1M x 32
Sense AMP
1M x 32
1M x 32
1M x 32
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Timing Register
Programming Register
LWCBR
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 May. 2003
K4S283232E-T
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
Input Function
Active on the positive going edge to sample all inputs.
CMOS SDRAM
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
11
, Column address : CA
0
~ CA
7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
CKE
Clock enable
A
0
~ A
11
Address
BA
0
~ BA
1
Bank select address
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM
DQ
0
~
31
V
DD
/V
SS
V
DDQ
/V
SSQ
Data input/output mask
Data input/output
Power supply/ground
Data output power/ground
No connection
/reserved for future use
N.C/RFU
Rev. 1.0 May. 2003
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