K6F1016S4A Family
Document Title
CMOS SRAM
64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
0.0
Initial Draft
- Specify CSP type to distinguish between uBGA and FP BGA
Finalize
- Change V
DR
: 1.0 to 1.5V
- Change I
DR
test condition : V
CC
=1.2 to 1.5V
Errata correction
Draft Date
November 4, 1998
Remark
Preliminary
1.0
February 26, 1999
Final
1.01
July 29, 1999
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
-1-
Revision 1.0
February 1999
K6F1016S4A Family
CMOS SRAM
64K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
FEATURES
•
•
•
•
•
•
GENERAL DESCRIPTION
The K6F1016S4A families are fabricated by SAMSUNG′s
advanced full CMOS process technology. The families support
industrial temperature range and 48 ball Chip Scale Package
for user flexibility of system design. The families also support
low data retention voltage for battery back-up operation with
low data retention current.
Process Technology: Full CMOS
Organization: 64K x16 bit
Power Supply Voltage: 2.3~2.7V
Low Data Retention Voltage: 1.5V(Min)
Three state output status and TTL Compatible
Package Type: 48-FBGA-6.00x7.00
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed
Standby
(I
SB1
, Typ.)
0.5µA
Operating
(I
CC1
, Max)
4mA
PKG Type
K6F1016S4A-I
Industrial(-40~85°C)
2.3~2.7V
70
1)
/100ns
48-FBGA-6.00x7.00
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
1
2
3
4
5
6
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
A
LB
OE
A0
A1
A2
N.C
Vcc
Vss
Row
Addresses
Memory array
1024 rows
64
×
16 columns
B
I/O9
UB
A3
A4
CS
I/O1
Row
select
C
I/O10
I/O11
A5
A6
I/O2
I/O3
D
Vss
I/O12
N.C
A7
I/O4
Vcc
E
Vcc
I/O13
N.C
N.C
I/O5
Vss
I/O
1
~I/O
8
Data
cont
Data
cont
Data
cont
I/O Circuit
Column select
F
I/O15
I/O14
A14
A15
I/O6
I/O7
I/O
9
~I/O
16
G
I/O16
N.C
A12
A13
WE
I/O8
Column Addresses
H
N.C
A8
A9
A10
A11
N.C
48-CSP - Top View
Name
CS
OE
WE
A
0
~A
15
Function
Chip Select Input
Output Enable Input
Write Enable Input
Address Inputs
Name
Vcc
Vss
UB
LB
N.C.
Function
Power
Ground
Upper Byte(I/O
9
~
16
)
Lower Byte(I/O
1
~
8
)
No Connection
CS
OE
WE
UB
LB
Control Logic
I/O
1
~I/O
16
Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice
.
-2-
Revision 1.0
February 1999
K6F1016S4A Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
K6F1016S4A-FI70
K6F1016S4A-FI10
48-FBGA, 70ns, 2.5V
48-FBGA, 100ns, 2.5V
Function
CMOS SRAM
FUNCTIONAL DESCRIPTION
CS
H
X
1)
L
L
L
L
L
L
L
L
OE
X
1)
X
1)
H
H
L
L
L
X
1)
X
1)
X
1)
WE
X
1)
X
1)
H
H
H
H
H
L
L
L
LB
X
1)
H
L
X
1)
L
H
L
L
H
L
UB
X
1)
H
X
1)
L
H
L
L
H
L
L
I/O
1~8
High-Z
High-Z
High-Z
High-Z
Dout
High-Z
Dout
Din
High-Z
Din
I/O
9~16
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Dout
High-Z
Din
Din
Mode
Deselected
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Power
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
1. X means don
′
t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.2 to 3.0V
-0.2 to 3.6V
1.0
-55 to 150
-40 to 85
Unit
V
V
W
°C
°C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
-3-
Revision 1.0
February 1999
K6F1016S4A Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Note :
1. T
A
=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+1.0V in case of pulse width
≤
20ns.
3. Undershoot: -1.0V in case of pulse width
≤
20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CMOS SRAM
Symbol
Vcc
Vss
V
IH
V
IL
Min
2.3
0
2.0
-0.2
3)
Typ
2.5
0
-
-
Max
2.7
0
Vcc+0.2
2)
0.4
Unit
V
V
V
V
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Symbol
Test Conditions
V
IN
=Vss to Vcc
CS=V
IH
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS=V
IL
, V
IN
=V
IH
or V
IL
Cycle time=1µs, 100% duty, I
IO
=0mA, CS≤0.2V, V
IN
≤0.2V
or V
IN
≥
V
CC
-
0.2V
Cycle time=Min, I
IO
=0mA
,
100% duty, CS=V
IL,
V
IN
=V
IH
or V
IL
Min Typ Max Unit
-1
-1
-
-
-
-
2.0
-
-
-
-
-
-
-
-
-
-
0.5
1
1
2
4
30
0.4
-
0.3
2
1)
µA
µA
mA
mA
mA
V
V
mA
µA
I
LI
I
LO
I
CC
I
CC1
I
CC2
Average operating current
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current (CMOS)
V
OL
V
OH
I
SB
I
SB1
I
OL
= 0.5mA
I
OH
= -0.5mA
CS=V
IH
or LB=UB=V
IH
, Other inputs=V
IH
or V
IL
CS≥Vcc-0.2V or LB=UB≥Vcc-
0.2V, CS≤0.2V, Other inpu
ts=0~Vcc
1. Super low power product=1µA with special handling.
-4-
Revision 1.0
February 1999
K6F1016S4A Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.2 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.1V
Output load (See right): C
L
= 100pF+1TTL
C
L
=30pF+1TTL
CMOS SRAM
V
TM
3)
R
1
2)
C
L
1)
R
2
2)
1. Including scope and jig capacitance
2. R
1
=3070Ω
,
R
2
=3150Ω
3. V
TM
=1.8V
AC CHARACTERISTICS
(Vcc=2.3~2.7V, T
A
=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
UB, LB Access Time
Read
Chip select to low-Z output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
UB, LB Valid to End of Write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO
t
OE
t
BA
t
LZ
t
BLZ
t
OLZ
t
HZ
t
BHZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
BW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
70
-
-
-
-
10
5
5
0
0
0
10
70
60
0
60
60
55
0
0
30
0
5
70ns
Max
-
70
70
35
70
-
-
-
25
25
25
-
-
-
-
-
-
-
-
25
-
-
-
Min
100
-
-
-
-
10
5
5
0
0
0
15
100
80
0
80
80
70
0
0
40
0
5
100ns
Max
-
100
100
50
100
-
-
-
30
30
30
-
-
-
-
-
-
-
-
30
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
VDR
IDR
tSDR
tRDR
Test Condition
CS≥Vcc-0.2V
1)
Vcc= 1.5V, CS≥Vcc-0.2V
1)
See data retention waveform
Min
1.5
-
0
tRC
Typ
-
-
-
-
Max
2.7
1
-
-
Unit
V
µA
ns
1. CS≥Vcc-0.2V(CS controlled) or LB=UB≥Vcc-0.2V, CS≤0.2V(LB, UB controlled)
-5-
Revision 1.0
February 1999
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