M368L3313BT1
184pin Unbuffered DDR SDRAM MODULE
256MB DDR SDRAM MODULE
(32Mx64(16Mx64*2 bank) based on 16Mx8 DDR SDRAM)
Unbuffered 184pin DIMM
64-bit Non-ECC/Parity
Revision 0.8
Nov. 2000
Rev. 0.8 Nov. 2000
M368L3313BT1
Revision History
Revision 0 (Aug 1998)
1. First release for internal usage
184pin Unbuffered DDR SDRAM MODULE
Revision 0.1 (May. 1999)
1. Changed die revision from B-die to C-die
2. Changed DC/AC characteristics item from old version.
Revision 0.2 (Aug. 1999)
1. Changed die revision from C-die to B-die
2. Modified binning policy
From
To
-Z (133Mhz)
-Z (133Mhz/266Mbps@CL=2)
-8 (125Mhz)
-Y (133Mhz/266Mbps@CL=2.5)
-0 (100Mhz)
-0 (100Mhz/200Mbps@CL=2)
3.Modified the following AC spec values
From.
-Z
tAC
tDQSCK
tDQSQ
tDS/tDH
tCDLR
*1
tPRE
*1
tRPST
*1
tHZQ
*1
*1
To.
-0
+/- 1ns
+/- 1ns
+/- 0.75ns
0.75 ns
-Z
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
-Y
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
-0
+/- 0.8ns
+/- 0.8ns
+/- 0.6ns
0.6 ns
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/-0.8ns
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
2.5tCK-tDQSS
1tCK +/- 0.75ns
tCK/2 +/- 0.75ns
tCK/2 +/- 0.75ns
2.5tCK-tDQSS
1tCK +/- 1ns
tCK/2 +/- 1ns
tCK/2 +/- 1ns
: Changed description method for the same functionality. This means no difference from the previous version.
4.Changed the following AC parameter symbol From tDQCK To tAC
Output data access time from CK/CK
Revision 0.3 (Sept. 1999)
1. Changed the odering information.
1-1. Exclude KM mark.
From
KMM368...
1-2. PCB Revison
From
- Blank: 1st generation
-A
: 2nd generation
-B
: 2nd generation
Example:KMM368L3313BT
1-3. Modified binning policy
From
- 0 (100Mhz/200Mbps@CL=2)
- Z (133Mhz/266Mbps@CL=2)
- Y (133Mhz/266Mbps@CL=2.5)
To
M368.....
To
- 0: 1st gernation
- 1: 2nd generation
- 2: 3nd generation
M368L3313BT0
To
- A0 (100Mhz/200Mbps@CL=2)
- A2 (133Mhz/266Mbps@CL=2)
- B0 (133Mhz/266Mbps@CL=2.5)
Rev. 0.8 Nov. 2000
M368L3313BT1
Revision 0.4 (December. 1999)
184pin Unbuffered DDR SDRAM MODULE
1. Changed from 3.3V to 2.5V in VDDSPD power.
Revision 0.5 (April. 2000)
< Page 3 >
1. Changed from 1450mil to 1250mil in PCB height.
2. Changed pin 90 from WP to NC in pin configuration table.
3. Changed in pin configuration table as followings.
pin 16 : CK0 -> CK1
pin 17 : CK0 -> /CK1
pin 137 : CK1 -> CK0
pin 138 : CK1 -> /CK0
4. Removed WP in pin description.
< Page 4>
5. Changed Clock wiring as followings.
CK0 / CK0 6SDRAMs -> 4SDRAMs
CK1 / CK1 4SDRAMs -> 6SDRAMs
6. Changed bypassing to reflect common Vdd/Vddq plane.
7. Added A13, BA1.
8. Removed WP from serial PD.
< Page 5>
9.
Changed Power & DC operating condition.
Parameter
I/O Reference voltage
Input logic high voltage
Input logic low voltage
Input leakage current
Output High Current (V
OUT
= 1.95V)
Output Low Current (V
OUT
= 0.35V)
Symbol
Min
V
REF
V
IH
(DC)
V
IL
(DC)
I
I
I
OH
I
OL
1.15
From
Max
1.35
V
DDQ
+0.3
V
REF
-0.18
5
To
Min
0.49*VDDQ
V
REF
+0.15
-0.3
-2
-16.8
16.8
Max
0.51*VDDQ
V
DDQ
+0.3
V
REF
-0.15
2
V
REF
+0.18
-0.3
-5
-15.2
15.2
< Page 6 >
10. Added Overshoot/Undershoot spec
. Vih(max) = 4.2V, the overshoot voltage duration is
≤
3ns at VDD.
. Vil(min) =- 1.5V, the overshoot voltage duration is
≤
3ns at VSS.
< Page 6,7 >
11. Changed AC operating conditions as follows.
Parameter/Condition
Symbol
Min
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC)
Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC)
Input Differential Voltage, CK and CK inputs
VID(AC)
0.7
VREF + 0.35
VREF - 0.35
VDDQ+0.6
0.62
From
Max
Min
VREF + 0.31
VREF - 0.31
VDDQ+0.6
To
Max
Rev. 0.8 Nov. 2000
M368L3313BT1
184pin Unbuffered DDR SDRAM MODULE
< Page 7 >
12. Changed Input/Output capacitance as follows.
Parameter
Input capacitance(A
0
~ A
11
, BA
0
~ BA
1
,RAS,CAS, WE )
Input capacitance(CKE
0,
CKE
1
)
Input capacitance( CS
0
, CS
1
)
Input capacitance( CLK
0
, CLK
1,
CLK
2
)
Data & DQS input/output capacitance(DQ
0
~DQ
63
)
Input capacitance(DM
0
~DM
8
)
Symbol
Min
C
IN1
C
IN2
C
IN3
C
IN4
C
OUT
C
IN5
-
-
-
-
-
-
From
Max
90
62
55
38
16
16
Min
65
42
42
27
10
10
To
Max
81
50
50
34
13
13
< page 8, 9>
13. Changed AC parameters as follows.
Parameter
tDQSQ
tDV
from
+/- 0.5(PC266), +/- 0.6(PC200)
+/- 0.35tCK
to
+0.5(PC266), +0.6(PC200)
-
Removed
Comments
14. Added AC parameters as follows
-A2(PC266@CL=2)
Parameter
Symbol
Min
Output DQS valid window
tQH
tHPmin
-0.75ns
tCLmin
or
tCHmin
0.9
0.4
Max
-
Min
tHPmin
-0.75ns
tCLmin
or
tCHmin
0.9
0.4
Max
-
Min
tHPmin
-1.0ns
tCLmin
or
tCHmin
0.9
0.4
Max
-
-B0(PC266@CL=2.5)
-A0(PC200@CL=2)
Clock half period
QFC setup to first DQS edge on reads
QFC hold after last DQS edge on reads
Write command to QFC delay on write
Write burst end to QFC delay on write
Write burst end to QFC delay on write
interrupted by Precharge
tHP
tQCS
tDQCH
tQCSW
tQCHW
tQCHWI
-
-
-
1.1
0.6
4.0
1.1
0.6
4.0
1.1
0.6
4.0
1.25ns
1.25ns
0.5tCK
1.5tCK
1.25ns
1.25ns
0.5tCK
1.5tCK
1.25ns
1.25ns
0.5tCK
1.5tCK
< Page 12>
15. Changed from 1450mil to 1250mil in Package dimension.
Revision 0.6 (June. 2000)
1. Changed PCB version from T0 to T1.
Rev. 0.8 Nov. 2000
M368L3313BT1
184pin Unbuffered DDR SDRAM MODULE
Revision 0.7 (October. 2000)
1.Added DC target spec values.
2.Deleted tDAL in AC parameter X.
Revision 0.8 (November. 2000)
1.Changed component placement on module PCB in package dimesions.
Rev. 0.8 Nov. 2000