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534BB000281DG

Description
LVDS Output Clock Oscillator
CategoryPassive components    oscillator   
File Size1MB,12 Pages
ManufacturerSilicon Laboratories Inc
Download Datasheet Parametric View All

534BB000281DG Overview

LVDS Output Clock Oscillator

534BB000281DG Parametric

Parameter NameAttribute value
MakerSilicon Laboratories Inc
Reach Compliance Codeunknow
Oscillator typeLVDS
Si534
R
EVISION
D
Q
UAD
F
R E Q U E N C Y
C
RYSTAL
O
S C I L L A T O R
(XO)
(10 M H
Z TO
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
Four selectable output frequencies
®
3rd generation DSPLL with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
Description
The Si534 quad frequency XO utilizes Silicon Laboratories’ advanced
DSPLL
®
circuitry to provide a low jitter clock at high frequencies. The Si534
is available with any-rate output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is
required for each output frequency, the Si534 uses one fixed crystal to
provide a wide range of output frequencies. This IC-based approach allows
the crystal resonator to provide exceptional frequency stability and reliability.
In addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low jitter clocks in noisy environments
typically found in communication systems. The Si534 IC-based XO is factory
configurable for a wide variety of user specifications including frequency,
supply voltage, output format, and temperature stability. Specific
configurations are factory programmed at time of shipment, thereby
eliminating long lead times associated with custom oscillators.
FS[1]
7
NC
1
6
V
DD
OE
2
5
CLK–
GND
3
8
FS[0]
4
CLK+
(LVDS/LVPECL/CML)
FS[1]
7
NC
1
6
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
OE
2
5
NC
FS[1]
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
GND
FS[0]
3
8
FS[0]
4
CLK
(CMOS)
OE
GND
Rev. 1.3 4/13
Copyright © 2013 by Silicon Laboratories
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