HYMP31GP72CUP4M-C5 datasheet, PDF

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HYMP31GP72CUP4M-C5: DescriptionDDR DRAM Module, 1GX72, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240; Categorystorage storage; File Size250KB，32 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

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HYMP31GP72CUP4M-C5 Overview

DDR DRAM Module, 1GX72, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240

HYMP31GP72CUP4M-C5 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SK Hynix
Parts packaging code	DIMM
package instruction	DIMM, DIMM240,40
Contacts	240
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	0.5 ns
Other features	AUTO/SELF REFRESH; SEATED HGT-NOM; WD-MAX
Maximum clock frequency (fCLK)	266 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N240
length	133.35 mm
memory density	77309411328 bi
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	240
word count	1073741824 words
character code	1000000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	55 °C
Minimum operating temperature
organize	1GX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM240,40
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	260
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	30 mm
self refresh	YES
Maximum standby current	1.747 A
Maximum slew rate	5.96 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	7.55 mm

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240pin DDR2 MetaSDRAM Registered DIMM based on 1Gb version C

This Hynix 8GB DDR2 MetaSDRAM Registered DIMM contains standard Hynix C-version 1Gb DDR2

SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. The module is capable

of operating at PC2-4200(DDR2-533) data rate.

The MetaRAM 8GB DDR2 SDRAM module operates in registered mode, where the address and command

inputs clocked into register chips on the rising edge of the clock signal. The registered mode adds a one

clock cycle delay to all the commands. A phase-lock loop (PLL) chip on the module receives the differential

clock signal from the motherboard and re-drives multiple copies to the register adn buffer chips on the

module. The register and PLL chips minimize the loading on the address, control, and clock lines on the

motherboard. The PLL used on the MetaRAM 8GB R-DIMM is fully compliant with the JEDEC specications.

The MetaRAM 8GB R-DIMM also has an on-board SPD EEPROM. The SPD chip contains 256byte, the first

128 of which are used by the module vendors to specify information like module type, DRAM organization,

DRAM timing, and module manufacturer. The last 128 bytes are not programmed, and may be used the

customer. The SPD chip may be read via a standard I2C bus using the SCL, SDA, and SA[2:O] signals. The

write protect (WP) pin is tied to ground on the module to enable writes to the SPD.

The MetaRAM 8GB RDIMM features WakeOneUse power saving technology capable of lowering the power

consumption of the modules under all workloads. The modules support additive latency (AL). WakeOnUse

is disabled when additive latency is enabled.

The 8GB MetaSDRAM RDIMM also provides higher sustained bandwidth than a standard RDIMM. The

modules are designed with no tFAW restriction (i.e. tFAW = 4 * tRRD). In addition, the MetaSDRAM

RDIMM provides 0-cycle turnaround for reads to the two ranks of the DIMM. That is, the memory control-

ler can schedule a read to one rank of a DIMM followed immediately (i.e. with 0-cycle gap or delay) by a

read to the other rank of the same DIMM. Similarly, the MetaSDRAM RDIMM provides 0-cycle turnaround

for writes to the two ranks of the DIMM. Since tFAW and intra-DIMM rank-rank turnaround time are not

part of the DDR2 SPD specification, BIOS must recognize the MetaSDRAM RDIMM at boot time and

explicitly configure the memory controller to take advantage of the tFAW and 0-cycle rank-rank

turnaround capabilities of the MetaSDRAM RDIMM. Please refer to the SPD application note on how BIOS

may recognize a Hynix’s MetaSDRAM RDIMM.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.2 / Sep. 2008

HYMP31GP72CUP4M-C5 Related Products

	HYMP31GP72CUP4M-C5	HYMP31GP72CUP4-C6
Description	DDR DRAM Module, 1GX72, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 1GX72, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240
Is it Rohs certified?	conform to	conform to
Maker	SK Hynix	SK Hynix
Parts packaging code	DIMM	DIMM
package instruction	DIMM, DIMM240,40	DIMM, DIMM240,40
Contacts	240	240
Reach Compliance Code	unknow	unknown
ECCN code	EAR99	EAR99
access mode	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
Maximum access time	0.5 ns	0.5 ns
Other features	AUTO/SELF REFRESH; SEATED HGT-NOM; WD-MAX	AUTO/SELF REFRESH; SEATED HGT-NOM; WD-MAX
Maximum clock frequency (fCLK)	266 MHz	266 MHz
I/O type	COMMON	COMMON
JESD-30 code	R-XDMA-N240	R-XDMA-N240
length	133.35 mm	133.35 mm
memory density	77309411328 bi	77309411328 bit
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE
memory width	72	72
Number of functions	1	1
Number of ports	1	1
Number of terminals	240	240
word count	1073741824 words	1073741824 words
character code	1000000000	1000000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	55 °C	55 °C
organize	1GX72	1GX72
Output characteristics	3-STATE	3-STATE
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM
Encapsulate equivalent code	DIMM240,40	DIMM240,40
Package shape	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	260	260
power supply	1.8 V	1.8 V
Certification status	Not Qualified	Not Qualified
refresh cycle	8192	8192
Maximum seat height	30 mm	30 mm
self refresh	YES	YES
Maximum standby current	1.747 A	1.747 A
Maximum slew rate	5.96 mA	5.96 mA
Maximum supply voltage (Vsup)	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V
surface mount	NO	NO
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal form	NO LEAD	NO LEAD
Terminal pitch	1 mm	1 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	20	20
width	7.55 mm	7.55 mm

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