Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES;
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR
NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
SMSC/Non-SMSC Register Sets (Rev.
02-27-04)
Page 2
SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
LPC47M172 Datasheet Revision History
REVISION LEVEL
AND DATE
Rev. 02-27-04
Rev. 02-27-04
Rev. 02-27-04
SECTION/FIGURE/ENTRY
Table 12.2 - S3-S5 Standby Current, page
201
Ordering Information
Table 6.1 - Super I/O Block Logical Device
Number and Addresses, page 33
Chapter 1 - General Description, page 12
Chapter 12 - Electrical Characteristics,
page 196
Section 3.1 - Buffer Name Descriptions,
page 23
Table 3.1 - LPC47M172 Pin Description,
page 15
Table 6.1 - Super I/O Block Logical Device
Number and Addresses, page 33
Table 7.31 - Voltage Translation DDC Pins,
page 137
Figure 7.10 - VGA DDC Voltage
Translation Circuit, page 139
Table 7.34 - SMBus Isolation Pins, page
139
Figure 7.11 - SMBUS Isolation Circuit,
page 140
Table 12.1 - Operational DC
Characteristics, page 196
Table 7.7 - Programming for Configuration
Register B (Bits 5:3), page 106; Table 7.8 -
Programming for Configuration Register B
(Bits 2:0), page 106
Table 11.2 - LPC47M172 Configuration
Register Summary, page 178
Table 11.3 - Chip Level Registers, page
180
CORRECTION
Added note above table.
Added.
Revised heading to include “standard
SMSC” and “non-standard SMSC” register
sets.
Revised General Description adding AMI
TM
BIOS to keyboard interface.
Lead Temperature Range, lead and lead-
free; reference to spec name J-STD-020B.
Added I0_SW.
Buffer names revised for pins 87 – 90,
113 – 116.
Note 8 under table revised.
Added table.
Replaced buffer IOD8 with IO_SW.
Revised figure.
Replaced buffer IOD8 with IO_SW.
First paragraph under table revised.
Revised figure.
Added IO_SW buffer and description;
updated parameters for Icc and Itr.
Titles added to tables.
Rev. 02-26-04
Rev. 02-23-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Chapter 2 - Pin Layout, page 13
Table 3.1 - LPC47M172 Pin Description,
page 15
Chapter 8 Power Control Runtime
Registers, page 151
Chapter 9 GPIO Runtime Registers, page
158
Chapter 10 Runtime Register Block
Runtime Registers, page 162
Table 11.3 - Chip Level Registers, page
180
Value of TEST 7 reg for LD_NUM=1
changed to 0x01.
Definition of TEST 7 value:
Default = 0x00 (when pin 117 is NC), 0x01
(when pin 117 is connected to VTR) on
VCC POR, VTR POR, and HARD RESET
Note for pin 117
No Connect Pin 117,
Pin 117 described in Note 11.
Table added.
Table added.
Added paragraph describing runtime
registers tables.
Register 0x29
SMSC/Non-SMSC Register Sets (Rev.
02-27-04)
Page 3
SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table Of Contents
LPC47M172 Datasheet Revision History ................................................................................................. 3
Chapter 1
Chapter 2
Chapter 3
3.1
3.2
3.3
3.4
General Description.............................................................................................................. 12
Description of Pin Functions ................................................................................................ 15
Buffer Name Descriptions ..........................................................................................................................23
Pins With Internal Resistors .......................................................................................................................24
Pins That Require External Resistors.........................................................................................................24
Default State of Pins...................................................................................................................................25
Power and Clock Functionality............................................................................................. 30
5.1
3 Volt Operation / 5 Volt Tolerance ............................................................................................................30
5.2
VCC Power ................................................................................................................................................30
Super I/O Registers....................................................................................................................................33
Floppy Disk Controller ................................................................................................................................38
Data Rate Select Register (DSR)........................................................................................................44
6.4.8
Main Status Register...........................................................................................................................46
6.4.9
Data Register (FIFO)...........................................................................................................................47
6.4.10
Digital Input Register (DIR)..............................................................................................................48
6.4.11
Configuration Control Register (CCR) .............................................................................................49
6.4.12
Status Register Encoding ................................................................................................................50
6.5
Modes of Operation....................................................................................................................................52
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
6.8
Data Transfer Termination .........................................................................................................................54
6.9
Result Phase..............................................................................................................................................54
Data Transfer Commands ......................................................................................................................63
6.11.1
Read Data .......................................................................................................................................63
6.12
Read Deleted Data .................................................................................................................................64
6.13
Read A Track..........................................................................................................................................65
Format A Track .......................................................................................................................................67
6.18
Control Commands.................................................................................................................................69
6.18.1
Read ID ...........................................................................................................................................69
Version ...................................................................................................................................................72
General ...............................................................................................................................................89
7.1.2
TX and RX FIFO Operation.................................................................................................................89
IBM XT/AT Compatible, Bi-Directional and EPP Modes.............................................................................92
7.4.1
Data Port .............................................................................................................................................92
7.4.2
Status Port ..........................................................................................................................................92
7.4.3
Control Port .........................................................................................................................................93
7.4.4
EPP Address Port ...............................................................................................................................94
7.4.5
EPP Data Port 0..................................................................................................................................94
7.4.6
EPP Data Port 1..................................................................................................................................94
7.4.7
EPP Data Port 2..................................................................................................................................94
7.4.8
EPP Data Port 3..................................................................................................................................95
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