Commercial/
Industrial
PEEL™ 22CV10AZ -25
CMOS Programmable Electrically Erasable Logic Device
Features
s
s
Ultra Low Power Operation
- V
CC
= 5 Volts ±10%
- Icc = 10 µA (typical) at standby
- Icc = 2 mA (typical) at 1 MHz
- t
PD
= 25ns.
CMOS Electrically Erasable Technology
- Superior factory testing
-
Reprogrammable in plastic package
-
Reduces retrofit and development costs
Development/Programmer Support
- Third party software and programmers
- ICT PLACE Development Software and PDS-3
programmer
s
Architectural Flexibility
-
133 product terms x 44 input AND array
-
Up to 22 inputs and 10 I/O pins
-
12 possible macrocell configurations
-
Synchronous preset, asynchronous clear
-
Independent output enables
-
Programmable clock source and polarity
-
24-pin DIP/SOIC/TSSOP and 28-pin PLCC
Application Versatility
-
Replaces random logic
-
Pin and JEDEC compatible with 22V10
-
Ideal for power-sensitive systems
s
s
General Description
The PEEL™22CV10AZ is a Programmable Electrically
Erasable Logic (PEEL™) device that provides a low power
alternative to ordinary PLDs. The PEEL™22CV10AZ is
available in 24-pin DIP SOIC, TSSOP and 28-pin PLCC
,
packages (see Figure 19).
A “zero-power” (100µA max. I
CC
) standby mode makes the
PEEL™22CV10AZ ideal for power sensitive applications
such as handheld meters, portable communication equip-
ment and laptop computers/ peripherals. EE-reprogramma-
bility provides the convenience of instant reprogramming
for development and a reusable production inventory mini-
mizing the impact of programming changes or errors. EE-
reprogrammability also improves factory testability, thus
ensuring the highest quality possible.
The PEEL™22CV10AZ is JEDEC file compatible with stan-
dard 22V10 PLDs. Eight additional configurations per mac-
rocell (a total of 12) are also available by using the “+”
software/programming option (i.e., 22CV10AZ+). The addi-
tional macrocell configurations allow more logic to be put
into every device, potentially reducing the design's compo-
nent count and lowering the power requirements even fur-
ther.
Development and programming support for the
PEEL™22CV10AZ is provided by popular third-party pro-
grammers and development software. ICT also offers free
PLACE development software and a low-cost development
system (PDS-3).
Figure 19 Pin Configuration
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Figure 19 Block Diagram
DIP
TSSOP
PLCC
SOIC
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PEEL™ 22CV10AZ
(OPTIONAL)
132
0
ASYNCHRONOUS CLEAR
(TO ALL MACROCELLS)
2
9
MACRO
CELL
I/O
(27)
I/CLK
(2)
10
20
MACRO
CELL
I/O
(26)
I
(3)
21
MACRO
CELL
33
I/O
(25)
I
(4)
34
MACRO
CELL
48
I/O
(24)
I
49
(5)
MACRO
CELL
65
I/O
(23)
I
(6)
66
MACRO
CELL
82
I/O
(21)
I
(7)
83
MACRO
CELL
97
I/O
(20)
I
(9)
98
MACRO
CELL
110
I/O
(19)
I
(10)
111
121
MACRO
CELL
I/O
(18)
I
(11)
124
130
I
(12)
131
MACRO
CELL
SYNCHRONOUS PRESET
(TO ALL MACROCELLS)
I/O
(17)
I
(13)
(16)
I
Figure 21 PEEL™22CV10AZ Logic Array Diagram
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PEEL™ 22CV10AZ
Function Description
The implements logic functions as sum-of-products expres-
sions in a programmable-AND/fixed-OR logic array. User-
defined functions are created by programming the connec-
tions of input signals into the array. User-configurable out-
put structures in the form of I/O macrocells further increase
logic flexibility.
When programming the PEEL™22CV10AZ, the device
programmer first performs a bulk erase to remove the previ-
ous pattern. The erase cycle opens every logical connec-
tion in the array. The device is configured to perform the
user-defined function by programming selected connec-
tions in the AND array. (Note that PEEL™ device program-
mers automatically program all of the connections on
unused product terms so that they will have no effect on the
output function).
Architecture Overview
The architecture is illustrated in the block diagram of Figure
19. Twelve dedicated inputs and 10 I/Os provide up to 22
inputs and 10 outputs for creating logic functions (see Fig-
ure 21). At the core of the device is a programmable electri-
cally-erasable AND array that drives a fixed OR array. With
this structure, the PEEL™22CV10AZ can implement up to
10 sum-of-products logic expressions.
Associated with each of the ten OR functions is an I/O mac-
rocell that can be independently programmed to one of four
different configurations in standard 22V10 mode, or any
one of 12 configurations using the special “Plus” mode. The
programmable macrocells allow each I/O to be used to cre-
ate sequential or combinatorial logic functions of active-
high or active-low polarity, while providing three different
feedback paths into the AND array.
Variable Product Term Distribution
The PEEL™22CV10AZ provides 120 product terms to
drive the 10 OR functions. These product terms are distrib-
uted among the outputs in groups of 8, 10, 12, 14, and 16
to form logical sums (see Figure 21). This distribution
allows optimum use of the device resources.
Programmable I/O Macrocell
The unique twelve-configuration output macrocell provides
complete control over the architecture of each output. The
ability to configure each output independently lets you to
tailor the configuration of the PEEL™22CV10AZ to the pre-
cise requirements of your design.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 20, consists of a D-
type flip-flop and two signal-select multiplexers. The config-
uration of the macrocell is determined by four EEPROM
bits that control the multiplexers. These bits determine the
output polarity, output type (registered or non-registered)
and input-feedback path (bidirectional I/O, combinatorial
feedback). Refer to Table 1. for details. Four of these mac-
rocells duplicate the functionality of the industry-standard
PAL22V10. (See Figure 21 and Table 1.)
AND/OR Logic Array
The programmable AND array of the PEEL™22CV10AZ
(shown in Figure 21) is formed by input lines intersecting
product terms. The input lines and product terms are used
as follows:
s
44 Input Lines:
– 24 input lines carry the true and complement of the
signals applied to the 12 input pins
– 20 additional lines carry the true and complement
values of feedback or input signals from the 10 I/Os
s
133 Product Terms:
– 120 product terms (arranged in 2 groups of 8, 10, 12,
14, and 16) are used to form sum of product functions
– 10 output enable terms (one for each I/O)
– 1 global synchronous preset term
– 1 global asynchronous clear term
– 1 programmable clock term
Figure 20 Block Diagram of the
PEEL™22CV10A I/O Macrocell
At each input-line/product-term intersection, there is an
EEPROM memory cell that determines whether or not
there is a logical connection at that intersection. Each prod-
uct term is essentially a 44-input AND gate. A product term
that is connected to both the true and complement of an
input signal will always be FALSE and therefore will not
affect the OR function that it drives. When all the connec-
tions on a product term are opened, a “don’t care” state
exists and that term will always be TRUE.
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PEEL™ 22CV10AZ
In addition to emulating the four PAL-type output structures
(configurations 3, 4, 9, and 10), The macrocell provides
eight additional configurations. Equivalent circuits for the
twelve macrocell configurations are illustrated in Figure 22.
These structures are accessed by specifying the
PEEL™22CV10A+ or PEEL™22CV10A++ option when
assembling the equations.
Output Polarity
Each macrocell can be configured to implement active-high
or active-low logic. Programmable polarity eliminates the
need for external inverters.
Output Enable
The output of each I/O macrocell can be enabled or dis-
abled under the control of its associated programmable out-
put enable product term. When the logical conditions
programmed on the output enable term are satisfied, the
output signal is propagated to the I/O pin. Otherwise, the
output buffer is switched into the high-impedance state.
Under the control of the output enable term, the I/O pin can
function as a dedicated input, a dedicated output, or a bi-
directional I/O. Opening every connection on the output
enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically false and the
I/O will function as a dedicated input.
Figure 21 Equivalent Circuits for the Four
Configurations of the I/O Macrocell
Input/Feedback Select
When configuring an I/O macrocell to implement a regis-
tered function (configurations 1 and 2 in Figure 21), the Q
output of the flip-flop drives the feedback term. When con-
figuring an I/O macrocell to implement a combinatorial out-
put (configurations 3 and 4 in Figure 21), the feedback term
is taken from the I/O pin. In this case, the pin can be used
as a dedicated input or a bi-directional I/O (Refer also to
Table 1.)
Table 1. PEEL™22CV10A Macrocell
Configuration Bits
Configuration
#
1
2
3
4
A
0
1
0
B
0
0
1
Input/Feedback
Select
Register
Feedback
Bi-Directional
I/O
Output Select
Programmable Clock Options
Active Low
Register
Active High
Active Low
Combinatorial
Active High
A unique feature of the PEEL™22CV10AZ is a program-
mable clock multiplexer that allows you to select true or
complement forms of either the input pin or a product-term
clock source. This feature can be accessed by specifying
the PEEL™22CV10A++ option when assembling the equa-
tions.
When creating a PEEL™ device design, the desired mac-
rocell configuration is generally specified explicitly in the
design file. When the design is assembled or compiled, the
macrocell configuration bits are defined in the last lines of
the JEDEC programming file.
Output Type
The signal from the OR array can be fed directly to the out-
put pin (combinatorial function) or latched in the D-type flip-
flop (registered function). The D-type flip-flop latches data
on the rising edge of the clock and is controlled by the glo-
bal preset and clear terms. When the synchronous preset
term is satisfied, the Q output of the register is set HIGH at
the next rising edge of the clock input. Satisfying the asyn-
chronous clear sets Q LOW, regardless of the clock state. If
both terms are satisfied simultaneously, the clear will over-
ride the preset.
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PEEL™ 22CV10AZ
Figure 22 Equivalent Circuits for the Twelve Configurations of the PEEL™22CV10AZ+ I/O Macrocell
Table 1. I/O Macrocell Equivalent Circuits
Configuration
#
1
2
3
4
5
6
7
8
9
10
11
12
A
0
1
0
1
0
1
0
1
0
1
0
1
B
0
0
1
1
0
0
1
1
0
0
1
1
C
1
1
0
0
1
1
1
1
0
0
1
1
D
0
0
0
0
1
1
1
1
0
0
0
0
Input/Feedback Select
Register
Bi-directional I/O
Output Select
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Combinatorial
Register
Combinatorial Feedback
Combinatorial
Register
Register Feedback
Combinatorial
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