ATF280F
Rad-Hard Reprogrammable FPGA
DATASHEET
Features
SRAM-based FPGA designed for Space use
280K equivalent ASIC gates
14,400 cells ( two 3-input LUT or one 4-input LUT, one DFF)
Unlimited reprogrammability
SEE-hardened (Configuration RAM, FreeRAM
TM
, DFF, JTAG, I/O buffers)
Rad Hard by Design - No need for mitigation techniques during design
115,200 bits of distributed RAM
Organized in 32x4 blocks of RAM
Independent of Logic Cells
Single/Dual port capability
FreeRAM™
Global reset option
8 global clocks and 4 fast clocks
8 LVDS transceivers and 8 LVDS receivers
Cold-sparing and PCI-compliant I/Os
Flexible configuration modes
Master/Slave capability
Serial/Parallel capability
Check of the data during FPGA configuration
Self Integrity Check (SIC) of the configuration during FPGA operation
Performance
50MHz system performance
10ns 32X4 FreeRAM™ access time
Operating range
Voltages
1.65V to 1.95V (Core)
3V to 3.6V (Clustered I/Os)
Temperature
- 55°C to +125°C
Radiation performance
Total dose tested up to 300 krads (Si)
No single event latch-up below a LET of 95 MeV/mg/cm2
ESD better than 2000V for I/O and better than 1000V for LVDS
Quality grades
QML-Q or V
ESCC
Ceramic packages
7750HAERO11/15
256-pin CQFP (148 I/Os, 8 LVDS Tx and 8 LVDS Rx)
352-pin CQFP (249 I/Os, 8 LVDS Tx and 8 LVDS Rx)
472-pin CCGA (308 I/Os, 8 LVDS Tx and 8 LVDS Rx)
Weight: 14.9g (CCGA Package)
Design Kit including
Evaluation board
Software design tools
ISP probe
Description
The ATF280F is a radiation-hardened reprogrammable FPGA, especially designed for
space applications. For low-power consumption applications, the ATF280F is a new
device offering many advantages.
The ATF280F supports an innovative built-in SEU protection, which eliminates the need
for Triple-Module-Redundancy (TMR). Its re-programmability makes multiple design
iterations possible.
The Development Kit enables you to evaluate the ATF280F quickly and economically,
running simple demonstrations as well as your complete applications. Throughout your
development, from concept to final integration, Atmel provides the tools and support to
help you successfully integrate your application into the ATF280F.
The ATF280F is available in CCGA/CLGA 472 packages and features up to 308 standard
I/Os and 16 LVDS I/Os for the user application. The CQFP256 and CQFP352 packages
are also available for applications requiring fewer I/O’s.
Table 1.
Function
Available ASIC Gates (50% typ. routable)
Rows x Columns
Core Cells
RAM Bits
I/O max
ATF280F Summary
ATF280F
280K
120x120
14 400
115 200
308
Figure 2.
ATF280F
ATF280F Overview
POR
User I/O
FPGA Core
Configuration
SRAM
Configuration
control
Boundary
Scan
Controller
LVDS
Interface
Differential
Clocks
Configuration
Self Internal
Checker
Configuration
Load Checker
ATF280F [DATASHEET]
7750HAERO11/15
2
Table of Contents
1. Glossary............................................................................................. 6
2. Pin Description ................................................................................... 7
2.1
2.2
2.3
2.4
2.5
2.6
General Purpose IOs ........................................................................................ 7
Configuration Interface ...................................................................................... 7
LVDS Interface .................................................................................................. 9
Clocks Interface ................................................................................................ 9
JTAG ............................................................................................................... 9
Power Supply .................................................................................................. 10
3. Architecture ...................................................................................... 11
3.1
3.2
FPGA Core ..................................................................................................... 11
Configuration Logic ......................................................................................... 13
3.2.2
POR
........................................................................................... 13
3.2.3
Configuration Control ........................................................................ 13
3.2.4
Configuration SRAM ......................................................................... 13
3.2.5
Configuration Load Checker ............................................................. 13
3.2.6
Configuration Self Internal Checker .................................................. 14
User I/O........................................................................................................... 14
LVDS I/O ......................................................................................................... 14
Clock ............................................................................................................. 14
JTAG ............................................................................................................. 14
3.3
3.4
3.5
3.6
4. Operating Modes / Lifephases ......................................................... 15
4.2
Power-On Reset.............................................................................................. 16
4.2.1
Description ........................................................................................ 16
4.2.2
Pin Function Availability .................................................................... 16
Manual Reset .................................................................................................. 17
4.3.1
Description ........................................................................................ 17
4.3.2
Pin Function Availability .................................................................... 17
Mode Sampling ............................................................................................... 18
4.4.1
Description ........................................................................................ 18
4.4.2
Pin Function Availability .................................................................... 18
Idle
............................................................................................................. 19
4.5.1
Description ........................................................................................ 19
4.5.2
Pin Function Availability .................................................................... 19
Configuration Download .................................................................................. 20
4.6.1
Description ........................................................................................ 20
4.6.2
Pin Function Availability .................................................................... 20
Run ............................................................................................................. 21
4.7.1
Description ........................................................................................ 21
4.7.2
Pin Function Availability .................................................................... 21
4.3
4.4
4.5
4.6
4.7
5. Configuration Download ................................................................... 22
5.2
Serial Configuration......................................................................................... 23
5.2.1
Bitstream Structure ........................................................................... 23
5.2.1.2
Null Byte.......................................................................... 24
5.2.1.3
Preamble......................................................................... 24
5.2.1.4
Configuration Register .................................................... 24
5.2.1.5
Number of Windows ........................................................ 24
5.2.1.6
Data Window................................................................... 24
5.2.1.7
Checksum Window ......................................................... 24
5.2.1.8
Recurrent Checksum ...................................................... 25
5.2.1.9
Postamble ....................................................................... 25
Master Mode – Mode 0 ................................................................................... 26
5.3.2
Configuration Download from Power-On Reset in mode 0 ............... 26
5.3.3
Configuration Download from Manual Reset in mode 0 .................... 29
5.3
ATF280F [DATASHEET]
7750HAERO11/15
3
5.4
5.5
5.3.4
Restart of Configuration Download in mode 0 .................................. 31
Slave Modes ................................................................................................... 33
5.4.1
Mode 1 ........................................................................................... 33
5.4.1.2
Power-On Reset in mode 1 ............................................. 33
5.4.1.3
Manual Reset in mode 1 ................................................. 36
5.4.1.4
Configuration Download in mode 1 ................................. 37
5.4.2
Mode 7 ........................................................................................... 40
5.4.2.2
Power-On Reset in mode 7 ............................................. 40
5.4.2.3
Manual Reset in mode 7 ................................................. 43
5.4.2.4
Configuration Download in mode 7 ................................. 45
5.4.3
Data Link Protection.......................................................................... 47
5.4.3.2
Low level Errors management ........................................ 48
5.4.3.3
Checksum Errors management ...................................... 49
Parallel Configuration ...................................................................................... 51
5.5.1
Bitstream Structure ........................................................................... 51
5.5.2
Slave Modes ..................................................................................... 51
5.5.2.1
Mode 2 ............................................................................ 51
5.5.2.2
Mode 6 ............................................................................ 51
5.5.3
Data Link Protection.......................................................................... 52
5.5.3.2
Low level Errors management ........................................ 54
5.5.3.3
Checksum Errors management ...................................... 54
6. Configuration Integrity Management ................................................ 56
6.1
Check function ................................................................................................ 56
6.1.1
Description ........................................................................................ 56
6.1.2
Serial Modes ..................................................................................... 58
6.1.3
Parallel Modes .................................................................................. 58
6.1.4
Behavior ........................................................................................... 59
Self Integrity Checker function ........................................................................ 61
6.2.1
Description ........................................................................................ 61
6.2.2
Behavior ........................................................................................... 62
6.2
7. FreeRam
TM
....................................................................................... 63
8. General Purpose Interface ............................................................... 65
8.2
8.3
8.4
Direction Configuration.................................................................................... 66
Pull-up/Pull-down ............................................................................................ 66
Output Configuration ....................................................................................... 66
8.4.1
Standard Configuration ..................................................................... 66
8.4.2
Open Source..................................................................................... 66
8.4.3
Open Drain ....................................................................................... 67
8.4.4
Output drive ...................................................................................... 67
Input Configuration .......................................................................................... 67
8.5.1
Schmitt ........................................................................................... 67
8.5.2
Delays ........................................................................................... 67
8.5.3
JTAG compliance ............................................................................. 68
8.5
9. LVDS Interface................................................................................. 69
10. Clock System ................................................................................... 70
10.2
10.3
Global Clock .................................................................................................... 71
Fast Clock ....................................................................................................... 71
11. Reset System................................................................................... 72
12. Power Supply Management ............................................................. 73
12.1
12.2
12.3
Cold sparing .................................................................................................... 73
Power sequencing........................................................................................... 73
Power-On Management .................................................................................. 74
13. JTAG
............................................................................................ 75
ATF280F [DATASHEET]
7750HAERO11/15
4
13.1
13.2
Overview ......................................................................................................... 75
TAP Architecture ............................................................................................. 76
13.2.2 TAP Instructions ............................................................................... 76
13.2.2.2 BYPASS.......................................................................... 76
13.2.2.3 EXTEST .......................................................................... 77
13.2.2.4 SAMPLE/PRELOAD ....................................................... 77
13.2.2.5 IDCODE .......................................................................... 77
13.2.3 TAP Controller .................................................................................. 77
13.2.4 TAP Data Registers .......................................................................... 78
13.2.4.1 Bypass Register .............................................................. 78
13.2.4.2 Device ID register ........................................................... 79
14. Register Description ......................................................................... 80
14.2
Description ...................................................................................................... 80
15. Package Information ........................................................................ 83
15.1
Packages Outline ............................................................................................ 83
15.1.1 CCGA 472 outline ............................................................................. 83
15.1.2 QFP 352 outline ................................................................................ 84
15.1.3 QFP 256 outline ................................................................................ 85
Pin Assignment ............................................................................................... 86
15.2.1 Core Power and Ground Cluster....................................................... 86
15.2.2 IO clusters......................................................................................... 87
15.2.3 LVDS clusters ................................................................................... 95
15.2
16. Electrical Characteristics .................................................................. 96
16.1
16.2
16.3
16.4
16.5
Absolute Maximum Ratings ............................................................................ 96
Operating Range ............................................................................................. 96
DC characteristics ........................................................................................... 97
LVDS AC/DC characteristics ........................................................................... 98
AC parameters .............................................................................................. 100
17. Ordering Information ...................................................................... 105
17.1
17.2
ATF280F Ordering Codes ............................................................................. 105
ATF280F Evaluation Kit Ordering Codes ...................................................... 105
18. Revision History ............................................................................. 106
19. Errata .......................................................................................... 107
19.1
19.2
Erratum 1: JTAG functionality ....................................................................... 107
Erratum 2: TRST JTAG pin ........................................................................... 107
ATF280F [DATASHEET]
7750HAERO11/15
5
NXP MCU
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