DF2B5M4SL
ESD Protection Diodes
Silicon Epitaxial Planar
DF2B5M4SL
1. Applications
•
ESD Protection
This product is designed for protection against electrostatic discharge (ESD) and is not intended for any other
purpose, including, but not limited to, voltage regulation.
Note:
2. Packaging and Internal Circuit
1: Pin 1
2: Pin 2
SL2
3. Absolute Maximum Ratings (Note) (Unless otherwise specified, T
a
= 25
)
Characteristics
Electrostatic discharge voltage (IEC61000-4-2)(Contact)
Electrostatic discharge voltage(IEC61000-4-2)(Air)
Peak pulse power(tp = 8/20
µS)
Peak pulse current(tp = 8/20
µS)
Junction temperature
Storage temperature
P
PK
I
PP
T
j
T
stg
(Note 2)
Symbol
V
ESD
Note
(Note 1)
Rating
±20
±20
30
2
150
-55 to 150
W
A
Unit
kV
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: According to IEC61000-4-2.
Note 2: According to IEC61000-4-5.
Note:
Start of commercial production
©2015 Toshiba Corporation
1
2015-09
2015-12-11
Rev.1.0
DF2B5M4SL
4. Electrical Characteristics (Unless otherwise specified, T
a
= 25
)
V
RWM
: Working peak reverse
voltage
V
BR
: Reverse breakdown voltage
I
BR
: Reverse breakdown current
I
R
: Reverse current
V
C
: Clamp voltage
I
PP
: Peak pulse current
R
DYN
: Dynamic resistance
Fig. 4.1 Definitions of Electrical Characteristics
Characteristics
Working peak reverse voltage
Reverse breakdown voltage
Reverse current
Clamp voltage
Clamp voltage
Dynamic resistance
Total capacitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
R
DYN
C
t
Note
Test Condition
I
BR
= 1 mA
V
RWM
= 3.6 V
Min
4.0
Typ.
5.0
7.5
10
17
24
0.5
0.2
Max
3.6
6.0
0.1
15
0.3
Unit
V
V
µA
V
V
Ω
pF
(Note 1)
(Note 2)
(Note 2)
(Note 3)
I
PP
= 1 A
I
PP
= 2 A
I
TLP
= 16 A
I
TLP
= 30 A
V
R
= 0 V, f = 1 MHz
Note 1: Based on IEC61000-4-5 8/20
µs
pulse.
Note 2: TLP parameter: Z0 = 50
Ω,
tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns,
extraction of dynamic resistance using a least-squares fit of TLP characteristics at I
PP
between 8 A to 16 A.
Note 3: Guaranteed by design.
©2015 Toshiba Corporation
2
2015-12-11
Rev.1.0
DF2B5M4SL
5. Marking
Fig. 5.1 Marking
6. Land Pattern Dimensions (for reference only)
Fig. 6.1 Land Pattern Dimensions (Unit: mm)
©2015 Toshiba Corporation
3
2015-12-11
Rev.1.0
DF2B5M4SL
7. Characteristics Curves (Note)
Fig. 7.1 I - V
Fig. 7.2 I
R
- V
R
Fig. 7.3 C
t
- V
R
Note:
Fig. 7.4 C
t
- f
The above characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
©2015 Toshiba Corporation
4
2015-12-11
Rev.1.0
DF2B5M4SL
8. Clamp Voltage V
C
- Peak Pulse Current (I
PP
) (Note)
Fig. 8.1 V
C
- I
PP
Fig. 8.2 Based on IEC61000-4-5 8/20
µ
s pulse.
(Ed.2)
Fig. 8.3 TLP
Note:
The above characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
©2015 Toshiba Corporation
5
2015-12-11
Rev.1.0
京公网安备 11010802033920号
EEWORLD
